1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2009 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t;
8
9   integer p_i;     // signal type IData
10   reg [15:0] p_s;  // signal type SData
11   reg [7:0] p_c;   // signal type CData
12   real p_r;        // signal type double
13   reg [7*8:1] p_str;
14   string      sv_str;
15   reg [7*8:1] p_in;
16   string      sv_in;
17
18   initial begin
19      if ($test$plusargs("PLUS")!==1) $stop;
20      if ($test$plusargs("PLUSNOT")!==0) $stop;
21      if ($test$plusargs("PL")!==1) $stop;
22      //if ($test$plusargs("")!==1) $stop;  // Simulators differ in this answer
23      if ($test$plusargs("NOTTHERE")!==0) $stop;
24
25      p_i = 10;
26      if ($value$plusargs("NOTTHERE%d", p_i) !== 0) $stop;
27      if ($value$plusargs("NOTTHERE%0d", p_i) !== 0) $stop;
28      if (p_i !== 10) $stop;
29
30      p_i = 0;
31      if ($value$plusargs("INT=%d", p_i) !== 1) $stop;
32      if (p_i !== 32'd1234) $stop;
33
34      p_i = 0;
35      if ($value$plusargs("INT=%0d", p_i) !== 1) $stop;
36      if (p_i !== 32'd1234) $stop;
37
38      p_i = 0;
39      if ($value$plusargs("INT=%H", p_i)!==1) $stop;  // tests uppercase % also
40      if (p_i !== 32'h1234) $stop;
41
42      p_i = 0;
43      // Check octal and WIDTH
44      if (!$value$plusargs("INT=%o", p_i)) $stop;
45      if (p_i !== 32'o1234) $stop;
46
47      // Check handling of 'SData' type signals (Issue #1592)
48      p_s = 0;
49      if (!$value$plusargs("INT=%d", p_s)) $stop;
50      if (p_s !== 16'd1234) $stop;
51
52      // Check handling of 'CData' type signals (Issue #1592)
53      p_c = 0;
54      if (!$value$plusargs("INT=%d", p_c)) $stop;
55      if (p_c !== 8'd210) $stop;
56
57      // Check handling of 'double' type signals (Issue #1619)
58      p_r = 0;
59      if (!$value$plusargs("REAL=%e", p_r)) $stop;
60      $display("r='%e'", p_r);
61      if (p_r !== 1.2345) $stop;
62
63      p_r = 0;
64      if (!$value$plusargs("REAL=%f", p_r)) $stop;
65      $display("r='%f'", p_r);
66      if (p_r !== 1.2345) $stop;
67
68      p_r = 0;
69      if (!$value$plusargs("REAL=%g", p_r)) $stop;
70      $display("r='%g'", p_r);
71      if (p_r !== 1.2345) $stop;
72
73      p_str = "none";
74      if ($value$plusargs("IN%s", p_str)!==1) $stop;
75      $display("str='%s'",p_str);
76      if (p_str !== "T=1234") $stop;
77
78      sv_str = "none";
79      if ($value$plusargs("IN%s", sv_str)!==1) $stop;
80      $display("str='%s'",sv_str);
81      if (sv_str != "T=1234") $stop;
82
83      sv_str = "none";
84      $value$plusargs("IN%s", sv_str);
85      $display("str='%s'",sv_str);
86      if (sv_str != "T=1234") $stop;
87
88      p_in = "IN%s";
89`ifdef VERILATOR
90      p_in = $c(p_in); // Prevent constant propagation
91`endif
92      sv_str = "none";
93      if ($value$plusargs(p_in, sv_str)!==1) $stop;
94      $display("str='%s'",sv_str);
95      if (sv_str != "T=1234") $stop;
96
97      sv_str = "none";
98      if ($value$plusargs("IP%%P%b", p_i)!==1) $stop;
99      $display("str='%s'",sv_str);
100      if (p_i != 'b101) $stop;
101
102      sv_in = "INT=%d";
103`ifdef VERILATOR
104      if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation
105`endif
106      p_i = 0;
107      if ($value$plusargs(sv_in, p_i)!==1) $stop;
108      $display("i='%d'",p_i);
109      if (p_i !== 32'd1234) $stop;
110
111      // bug3131 - really "if" side effect test
112      p_i = 0;
113      if ($value$plusargs("INT=%d", p_i)) ;
114      if (p_i !== 32'd1234) $stop;
115
116      $write("*-* All Finished *-*\n");
117      $finish;
118   end
119endmodule
120