1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t(/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 int cyc = 0; 15 16 // Test loop 17 always @ (posedge clk) begin 18 cyc <= cyc + 1; 19 if (cyc == 10) begin 20 $strobe("[%0t] cyc=%0d", $time, cyc); 21 $strobe("[%0t] cyc=%0d also", $time, cyc); 22 end 23 else if (cyc == 17) begin 24 $strobeb(cyc, "b"); 25 end 26 else if (cyc == 18) begin 27 $strobeh(cyc, "h"); 28 end 29 else if (cyc == 19) begin 30 $strobeo(cyc, "o"); 31 end 32 else if (cyc == 22) begin 33 $strobe("[%0t] cyc=%0d new-strobe", $time, cyc); 34 end 35 else if (cyc == 24) begin 36 $monitoroff; 37 end 38 else if (cyc == 26) begin 39 $monitoron; 40 end 41 else if (cyc == 30) begin 42 $write("*-* All Finished *-*\n"); 43 $finish; 44 end 45 end 46endmodule 47