1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under The Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t; 8 9 timeunit 1ns; 10 timeprecision 1ps; 11 12 time t; 13 14 initial begin 15 t = 10ns; 16 17 $write("[%0t] In %m: Hi\n", $time); 18 $printtimescale; 19 $printtimescale(); 20 $printtimescale(t); 21 22 $write("Time: '%t' 10ns=%0t\n", $time, t); 23 $timeformat(-3, 0, "-my-ms", 8); 24 $write("Time: '%t' 10ns=%0t\n", $time, t); 25 $timeformat(-3, 1, "-my-ms", 10); 26 $write("Time: '%t' 10ns=%0t\n", $time, t); 27 $timeformat(-6, 2, "-my-us", 12); 28 $write("Time: '%t' 10ns=%0t\n", $time, t); 29 $timeformat(-9, 3, "-my-ns", 13); 30 $write("Time: '%t' 10ns=%0t\n", $time, t); 31 $timeformat(-12, 3, "-my-ps", 13); 32 $write("Time: '%t' 10ns=%0t\n", $time, t); 33 $timeformat(-15, 4, "-my-fs", 14); 34 $write("Time: '%t' 10ns=%0t\n", $time, t); 35 36 $write("*-* All Finished *-*\n"); 37 $finish; 38 end 39endmodule 40