1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under The Creative Commons Public Domain, for
4// any use, without warranty, 2021 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7`timescale 1ns/1ns
8module t;
9   p p ();
10
11   // Also check not-found modules
12   localparam NOT = 0;
13   if (NOT) begin
14      NotFound not_found(.*);
15   end
16
17   initial begin
18      $write("*-* All Finished *-*\n");
19      $finish;
20   end
21
22endmodule
23
24`timescale 1ns/1ns
25program p;
26endprogram
27
28`celldefine
29`timescale 1ns/1ns
30
31primitive a_udp(out, in);
32output out;
33input in;
34reg out;
35
36table
370       :   1;
381       :   0;
39?       :   ?;
40x       :   x;
41endtable
42endprimitive
43`endcelldefine
44
45`celldefine
46module c_not(in, out);
47input in;
48output out;
49assign out = !in1;
50endmodule
51`endcelldefine
52