1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2013 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t
8  (
9   input wire clk
10   );
11
12   integer    cyc; initial cyc = 0;
13   integer    unchanged; initial unchanged = 42;
14
15   always @ (posedge clk) begin
16      cyc <= cyc + 1;
17   end
18endmodule
19