1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2009 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7bit global_bit; 8 9module t (clk); 10 input clk; 11 integer cyc = 0; 12 13 typedef struct packed { 14 bit b1; 15 bit b0; 16 } strp_t; 17 18 typedef struct packed { 19 strp_t x1; 20 strp_t x0; 21 } strp_strp_t; 22 23 typedef union packed { 24 strp_t x1; 25 strp_t x0; 26 } unip_strp_t; 27 28 typedef bit [2:1] arrp_t; 29 typedef arrp_t [4:3] arrp_arrp_t; 30 31 typedef strp_t [4:3] arrp_strp_t; 32 33 typedef bit arru_t [2:1]; 34 typedef arru_t arru_arru_t [4:3]; 35 typedef arrp_t arru_arrp_t [4:3]; 36 typedef strp_t arru_strp_t [4:3]; 37 38 strp_t v_strp; 39 strp_strp_t v_strp_strp; 40 unip_strp_t v_unip_strp; 41 arrp_t v_arrp; 42 arrp_arrp_t v_arrp_arrp; 43 arrp_strp_t v_arrp_strp; 44 arru_t v_arru; 45 arru_arru_t v_arru_arru; 46 arru_arrp_t v_arru_arrp; 47 arru_strp_t v_arru_strp; 48 49 real v_real; 50 real v_arr_real [2]; 51 string v_string; 52 53 string v_assoc[string]; 54 initial v_assoc["key"] = "value"; 55 56 typedef struct packed { 57 logic [31:0] data; 58 } str32_t; 59 str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0 60 initial v_str32x2[0] = 32'hff; 61 initial v_str32x2[1] = 0; 62 63 typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t; 64 enumed_t v_enumed; 65 enumed_t v_enumed2; 66 typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t; 67 enumb_t v_enumb; 68 typedef struct packed { 69 enumb_t a; 70 enumb_t b; 71 } enumb2_str_t; 72 enumb2_str_t v_enumb2_str; 73 74 logic [7:0] unpacked_array[-2:0]; 75 76 bit LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; 77 78 p #(.PARAM(2)) p2 (); 79 p #(.PARAM(3)) p3 (); 80 81 p #(.PARAM(4)) a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed (); 82 83 always @ (posedge clk) begin 84 cyc <= cyc + 1; 85 v_strp <= ~v_strp; 86 v_strp_strp <= ~v_strp_strp; 87 v_unip_strp <= ~v_unip_strp; 88 v_arrp_strp <= ~v_arrp_strp; 89 v_arrp <= ~v_arrp; 90 v_arrp_arrp <= ~v_arrp_arrp; 91 v_real <= v_real + 0.1; 92 v_string <= cyc[0] ? "foo" : "bar"; 93 v_arr_real[0] <= v_arr_real[0] + 0.2; 94 v_arr_real[1] <= v_arr_real[1] + 0.3; 95 v_enumed <= v_enumed + 1; 96 v_enumed2 <= v_enumed2 + 2; 97 v_enumb <= v_enumb - 1; 98 v_enumb2_str <= {v_enumb, v_enumb}; 99 for (integer b=3; b<=4; b++) begin 100 v_arru[b] <= ~v_arru[b]; 101 v_arru_strp[b] <= ~v_arru_strp[b]; 102 v_arru_arrp[b] <= ~v_arru_arrp[b]; 103 for (integer a=3; a<=4; a++) begin 104 v_arru_arru[a][b] = ~v_arru_arru[a][b]; 105 end 106 end 107 v_str32x2[0] <= v_str32x2[0] - 1; 108 v_str32x2[1] <= v_str32x2[1] + 1; 109 if (cyc == 5) begin 110 $write("*-* All Finished *-*\n"); 111 $finish; 112 end 113 end 114endmodule 115 116module p; 117 parameter PARAM = 1; 118 initial global_bit = 1; 119endmodule 120