1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13
14   int   cyc;
15   reg   rstn;
16
17   parameter real  fst_gparam_real = 1.23;
18   localparam real fst_lparam_real = 4.56;
19   real            fst_real = 1.23;
20   integer         fst_integer;
21   bit             fst_bit;
22   logic           fst_logic;
23   int             fst_int;
24   shortint        fst_shortint;
25   longint         fst_longint;
26   byte            fst_byte;
27
28   parameter       fst_parameter = 123;
29   localparam      fst_lparam = 456;
30   supply0         fst_supply0;
31   supply1         fst_supply1;
32   tri0            fst_tri0;
33   tri1            fst_tri1;
34   tri             fst_tri;
35   wire            fst_wire;
36
37   logic [4:0] state;
38
39   Test test (/*AUTOINST*/
40              // Outputs
41              .state                    (state[4:0]),
42              // Inputs
43              .clk                      (clk),
44              .rstn                     (rstn));
45
46   // Test loop
47   always @ (posedge clk) begin
48      cyc <= cyc + 1;
49      if (cyc==0) begin
50         // Setup
51         rstn <= ~'1;
52      end
53      else if (cyc<10) begin
54         rstn <= ~'1;
55      end
56      else if (cyc<90) begin
57         rstn <= ~'0;
58      end
59      else if (cyc==99) begin
60         $write("*-* All Finished *-*\n");
61         $finish;
62      end
63   end
64
65endmodule
66
67
68module Test (
69          input              clk,
70          input              rstn,
71          output logic [4:0] state
72          );
73
74   logic [4:0]               state_w;
75   logic [4:0]               state_array [3];
76   assign state = state_array[0];
77
78   always_comb begin
79      state_w[4] = state_array[2][0];
80      state_w[3] = state_array[2][4];
81      state_w[2] = state_array[2][3] ^ state_array[2][0];
82      state_w[1] = state_array[2][2];
83      state_w[0] = state_array[2][1];
84   end
85
86   always_ff @(posedge clk or negedge rstn) begin
87      if (!rstn) begin
88         for (int i = 0; i < 3; i++)
89           state_array[i] <= 'b1;
90      end
91      else begin
92         for (int i = 0; i < 2; i++)
93           state_array[i] <= state_array[i+1];
94         state_array[2] <= state_w;
95      end
96   end
97
98endmodule
99