1$version Generated by VerilatedVcd $end 2$date Sat Mar 7 18:39:02 2020 3 $end 4$timescale 1ps $end 5 6 $scope module topa $end 7 $var wire 1 3 clk $end 8 $scope module t $end 9 $var wire 32 + c_trace_on [31:0] $end 10 $var wire 1 3 clk $end 11 $var wire 32 # cyc [31:0] $end 12 $scope module sub $end 13 $var wire 32 ; inside_sub_a [31:0] $end 14 $upscope $end 15 $upscope $end 16 $upscope $end 17$enddefinitions $end 18 19 20#10 21b00000000000000000000000000000001 # 22b00000000000000000000000000000000 + 2313 24b00000000000000000000000000000001 ; 25#10 26#15 27#15 2803 29#20 30#20 31b00000000000000000000000000000010 # 32b00000000000000000000000000000011 + 3313 34#25 35#25 3603 37#30 38#30 39b00000000000000000000000000000011 # 40b00000000000000000000000000000100 + 4113 42#35 43#35 4403 45#40 46#40 47b00000000000000000000000000000100 # 48b00000000000000000000000000000101 + 4913 50#45 51#45 5203 53#50 54#50 55b00000000000000000000000000000101 # 56b00000000000000000000000000000110 + 5713 58#55 59#55 6003 61#60 62#60 63b00000000000000000000000000000110 # 64b00000000000000000000000000000111 + 6513 66#65 67#65 6803 69#70 70#70 71b00000000000000000000000000000111 # 72b00000000000000000000000000001000 + 7313 74#75 75#75 7603 77#80 78#80 79b00000000000000000000000000001000 # 80b00000000000000000000000000001001 + 8113 82#85 83#85 8403 85#90 86#90 87b00000000000000000000000000001001 # 88b00000000000000000000000000001010 + 8913 90#95 91#95 9203 93#100 94#100 95b00000000000000000000000000001010 # 96b00000000000000000000000000001011 + 9713 98#105 99#105 10003 101#110 102#110 10313 104b00000000000000000000000000001011 # 105b00000000000000000000000000001100 + 106