1 // DESCRIPTION: Verilator: Verilog Test
2 //
3 // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
4 // redistribute it and/or modify it under the terms of either the GNU
5 // Lesser General Public License Version 3 or the Perl Artistic License
6 // Version 2.0.
7 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
8
9 // clang-format off
10 #include "verilatedos.h"
11 #include VM_PREFIX_INCLUDE
12 #include "Vt_trace_two_b.h"
13 #include "verilated.h"
14 #ifdef TEST_HDR_TRACE
15 # include "verilated_vcd_sc.h"
16 #endif
17 // clang-format on
18
19 // Compile in place
20 #include "Vt_trace_two_b__ALL.cpp"
21
22 // General headers
23 #include "verilated.h"
24 #include "systemc.h"
25
26 VM_PREFIX* ap;
27 Vt_trace_two_b* bp;
28
sc_main(int argc,char ** argv)29 int sc_main(int argc, char** argv) {
30 sc_signal<bool> clk;
31 sc_time sim_time(1100, SC_NS);
32 Verilated::commandArgs(argc, argv);
33 Verilated::traceEverOn(true);
34 Verilated::debug(0);
35 srand48(5);
36 ap = new VM_PREFIX("topa");
37 bp = new Vt_trace_two_b("topb");
38 ap->clk(clk);
39 bp->clk(clk);
40
41 #ifdef TEST_HDR_TRACE
42 VerilatedVcdSc* tfp = new VerilatedVcdSc;
43 ap->trace(tfp, 99);
44 bp->trace(tfp, 99);
45 tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
46 #endif
47 {
48 clk = false;
49 sc_start(10, SC_NS);
50 }
51 while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
52 clk = !clk;
53 sc_start(5, SC_NS);
54 }
55 if (!Verilated::gotFinish()) {
56 vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
57 }
58 ap->final();
59 bp->final();
60 #ifdef TEST_HDR_TRACE
61 if (tfp) tfp->close();
62 #endif
63
64 VL_DO_DANGLING(delete ap, ap);
65 VL_DO_DANGLING(delete bp, bp);
66 return 0;
67 }
68