1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11   input clk;
12
13   tri z0;
14   tri z1;
15
16   updown #(0) updown0 (.z(z0));
17   updown #(1) updown1 (.z(z1));
18
19   always @ (posedge clk) begin
20      if (z0 !== 0) $stop;
21      if (z1 !== 1) $stop;
22      $write("*-* All Finished *-*\n");
23      $finish;
24   end
25
26endmodule
27
28module updown #(parameter UP=0)
29   (inout z);
30   generate
31      if (UP) begin
32	 t_up sub (.z);
33      end
34      else begin
35	 t_down sub (.z);
36      end
37   endgenerate
38endmodule
39
40module t_up (inout tri1 z);
41endmodule
42
43module t_down (inout tri0 z);
44endmodule
45