1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2008 by Lane Brooks. 5// SPDX-License-Identifier: CC0-1.0 6 7module top (input A, input OE, output X, output Y, output Z); 8 9 pullup p1(Z); 10 assign Z = OE ? A : 1'bz; 11 12 pulldown p2(Y); 13 assign Y = OE ? A : 1'bz; 14 15 pass pass(.A(A), .OE(OE), .X(X)); 16 pullup_module p(X); 17endmodule 18 19module pass (input A, input OE, inout X); 20 io io(.A(A), .OE(OE), .X(X)); 21endmodule 22 23module io (input A, input OE, inout X); 24 assign X = (OE) ? A : 1'bz; 25endmodule 26 27module pullup_module (output X); 28 pullup p1(X); 29endmodule 30