1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11   input clk;
12
13   reg  a;
14   wire  o;
15   udp (o, a);
16
17   integer cyc;  initial cyc = 0;
18
19   // Test loop
20   always @ (posedge clk) begin
21      cyc <= cyc + 1;
22      a <= cyc[0];
23      if (cyc==0) begin
24      end
25      else if (cyc<90) begin
26	 if (a != !cyc[0]) $stop;
27      end
28      else if (cyc==99) begin
29	 $write("*-* All Finished *-*\n");
30	 $finish;
31      end
32   end
33
34endmodule
35
36primitive udp(o,a);
37   output o;
38   input  a;
39`ifdef verilator
40   wire   o = ~a;
41`else
42   table
43      //o a
44      0 :  1;
45      1 :  0;
46   endtable
47`endif
48endprimitive
49