1#!/usr/bin/env perl 2if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } 3# DESCRIPTION: Verilator: Verilog Test driver/expect definition 4# 5# Copyright 2003 by Wilson Snyder. This program is free software; you 6# can redistribute it and/or modify it under the terms of either the GNU 7# Lesser General Public License Version 3 or the Perl Artistic License 8# Version 2.0. 9# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 10 11scenarios(simulator => 1); 12 13top_filename("t/t_unopt_combo.v"); 14my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; 15 16compile( 17 verilator_flags2 => ["--stats $Self->{t_dir}/t_unopt_combo_isolate.vlt"], 18 ); 19 20if ($Self->{vlt_all}) { 21 file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i); 22 file_grep("$out_filename", qr/\<var fl="e23" loc=".*?" name="t.b" dtype_id="\d+" vartype="logic" origName="b" isolate_assignments="true"\/\>/i); 23 file_grep("$out_filename", qr/\<var fl="e104" loc=".*?" name="__Vfunc_t.file.get_31_16__0__Vfuncout" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout" isolate_assignments="true"\/\>/i); 24 file_grep("$out_filename", qr/\<var fl="e105" loc=".*?" name="__Vfunc_t.file.get_31_16__0__t_crc" dtype_id="\d+" vartype="logic" origName="__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc" isolate_assignments="true"\/\>/i); 25 file_grep("$out_filename", qr/\<var fl="e115" loc=".*?" name="__Vtask_t.file.set_b_d__1__t_crc" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc" isolate_assignments="true"\/\>/i); 26 file_grep("$out_filename", qr/\<var fl="e116" loc=".*?" name="__Vtask_t.file.set_b_d__1__t_c" dtype_id="\d+" vartype="logic" origName="__Vtask_t__DOT__file__DOT__set_b_d__1__t_c" isolate_assignments="true"\/\>/i); 27} 28 29execute( 30 ); 31 32ok(1); 331; 34