1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2007 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Outputs
9   x,
10   // Inputs
11   clk
12   );
13
14`ifdef ALLOW_UNOPT
15   /*verilator lint_off UNOPTFLAT*/
16`endif
17
18   input clk;
19   output x;   // Avoid eliminating x
20
21   reg x;
22   always @* begin
23      x = ~x;
24   end
25
26endmodule
27