1%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:15:15: Signal unoptimizable: Feedback to clock or circular logic: 't.x' 2 15 | wire [2:0] x; 3 | ^ 4 ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest 5 ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. 6 t/t_unoptflat_simple_2.v:15:15: Example path: t.x 7 t/t_unoptflat_simple_2.v:17:18: Example path: ASSIGNW 8 t/t_unoptflat_simple_2.v:15:15: Example path: t.x 9 ... Widest candidate vars to split: 10 t/t_unoptflat_simple_2.v:15:15: t.x, width 3, fanout 10, can split_var 11 ... Most fanned out candidate vars to split: 12 t/t_unoptflat_simple_2.v:15:15: t.x, width 3, fanout 10, can split_var 13 ... Suggest add /*verilator split_var*/ to appropriate variables above. 14%Error: Exiting due to 15