1%Error: t/t_var_bad_sv.v:8:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
2        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
3    8 |    reg do;
4      |        ^~
5%Error: t/t_var_bad_sv.v:9:14: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
6    9 |    mod mod (.do(bar));
7      |              ^~
8%Error: t/t_var_bad_sv.v:9:16: syntax error, unexpected '(', expecting ')'
9    9 |    mod mod (.do(bar));
10      |                ^
11%Error: Exiting due to
12