1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2019 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7// Legal with Verilog 1995 style ports
8
9module t
10  (/*AUTOARG*/
11   // Outputs
12   ok_o_w, ok_o_r, ok_o_ra, ok_or, ok_ow, ok_owa
13   );
14
15   output ok_o_w;
16   wire   ok_o_w;
17
18   output ok_o_r;
19   reg    ok_o_r;
20
21   output [1:0] ok_o_ra;
22   reg    [1:0] ok_o_ra;
23
24   output reg ok_or;
25
26   output wire ok_ow;
27
28   output wire [1:0] ok_owa;
29endmodule
30