1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2007 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t
8  (
9   /*AUTOARG*/
10   // Outputs
11   o, oi, og, org,
12   // Inputs
13   i, oi
14   );
15
16   reg    a;
17   reg    a;
18
19   integer l;
20   integer l;
21
22   bit     b;
23   bit     b;
24
25   output o;
26   output o;
27
28   input  i;
29   input  i;
30
31   output oi;
32   input  oi;
33
34   output og;
35   reg    og;
36   reg    og;
37
38   output reg org;
39   output reg org;
40
41   sub0 sub0(.*);
42   sub1 sub1(.*);
43   sub2 sub2(.*);
44   sub3 sub3(.*);
45endmodule
46
47module sub0
48  (
49   bad_duport,
50   bad_duport
51   );
52   output bad_duport;
53endmodule
54
55module sub1
56  (
57   bad_mixport,
58   output bad_mixport
59   );
60endmodule
61
62module sub2
63  (
64   output bad_reout_port
65   );
66   output bad_reout_port;
67endmodule
68
69module sub3
70  (output wire bad_rewire,
71   output reg bad_rereg
72   );
73   wire bad_rewire;
74   reg  bad_rereg;
75endmodule
76