1#!/usr/bin/env perl
2if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
3# DESCRIPTION: Verilator: Verilog Test driver/expect definition
4#
5# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
6# can redistribute it and/or modify it under the terms of either the GNU
7# Lesser General Public License Version 3 or the Perl Artistic License
8# Version 2.0.
9# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
10
11scenarios(simulator => 1);
12
13compile(
14    # Access is so we can dump waves
15    v_flags2 => [$Self->{vlt_all} ? '-trace' : ' +access+rwc'],
16    );
17
18execute(
19    check_finished => 1,
20    );
21
22if ($Self->{vlt_all}) {
23    file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
24    my $sig = quotemeta("bra[ket]slash/dash-colon:9");
25    file_grep("$Self->{obj_dir}/simx.vcd", qr/ $sig/);
26    file_grep("$Self->{obj_dir}/simx.vcd", qr/ other\.cyc /);
27    file_grep("$Self->{obj_dir}/simx.vcd", qr/ module mod\.with_dot /);
28    vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
29}
30
31ok(1);
321;
33