1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/);
8
9   integer i;
10   integer a_var;
11
12   sub sub ();
13
14   task nottask(); endtask
15   function int notfunc(); return 0; endfunction
16
17   initial begin
18      nf = 0;  // z not found
19      sub.subsubz.inss = 0;  // subsub not found
20      i = nofunc();  // nofunc not found
21      i = sub.nofuncs();  // nofuncs not found
22      notask();  // notask not found
23      a_var();  // Calling variable as task
24      $finish;
25   end
26endmodule
27
28module sub;
29   subsub subsub ();
30   function int notfuncs(); return 0; endfunction
31endmodule
32
33module subsub;
34   integer inss;
35endmodule
36