1<?xml version="1.0" ?>
2<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
3<verilator_xml>
4  <files>
5    <file id="a" filename="&lt;built-in&gt;" language="1800-2017"/>
6    <file id="b" filename="&lt;command-line&gt;" language="1800-2017"/>
7    <file id="c" filename="input.vc" language="1800-2017"/>
8    <file id="d" filename="t/t_var_port_xml.v" language="1800-2017"/>
9  </files>
10  <module_files>
11    <file id="d" filename="t/t_var_port_xml.v" language="1800-2017"/>
12  </module_files>
13  <cells>
14    <cell fl="d18" loc="d,18,8,18,11" name="mh2" submodname="mh2" hier="mh2"/>
15  </cells>
16  <cells>
17    <cell fl="d24" loc="d,24,8,24,11" name="mh5" submodname="mh5" hier="mh5"/>
18  </cells>
19  <cells>
20    <cell fl="d26" loc="d,26,8,26,11" name="mh6" submodname="mh6" hier="mh6"/>
21  </cells>
22  <cells>
23    <cell fl="d28" loc="d,28,8,28,11" name="mh7" submodname="mh7" hier="mh7"/>
24  </cells>
25  <cells>
26    <cell fl="d30" loc="d,30,8,30,11" name="mh8" submodname="mh8" hier="mh8"/>
27  </cells>
28  <cells>
29    <cell fl="d32" loc="d,32,8,32,11" name="mh9" submodname="mh9" hier="mh9"/>
30  </cells>
31  <cells>
32    <cell fl="d34" loc="d,34,8,34,12" name="mh10" submodname="mh10" hier="mh10"/>
33  </cells>
34  <cells>
35    <cell fl="d36" loc="d,36,8,36,12" name="mh11" submodname="mh11" hier="mh11"/>
36  </cells>
37  <cells>
38    <cell fl="d38" loc="d,38,8,38,12" name="mh12" submodname="mh12" hier="mh12"/>
39  </cells>
40  <cells>
41    <cell fl="d40" loc="d,40,8,40,12" name="mh13" submodname="mh13" hier="mh13"/>
42  </cells>
43  <cells>
44    <cell fl="d50" loc="d,50,8,50,12" name="mh17" submodname="mh17" hier="mh17"/>
45  </cells>
46  <cells>
47    <cell fl="d52" loc="d,52,8,52,12" name="mh18" submodname="mh18" hier="mh18"/>
48  </cells>
49  <cells>
50    <cell fl="d54" loc="d,54,8,54,12" name="mh19" submodname="mh19" hier="mh19"/>
51  </cells>
52  <cells>
53    <cell fl="d56" loc="d,56,8,56,12" name="mh20" submodname="mh20" hier="mh20"/>
54  </cells>
55  <cells>
56    <cell fl="d58" loc="d,58,8,58,12" name="mh21" submodname="mh21" hier="mh21"/>
57  </cells>
58  <netlist>
59    <module fl="d18" loc="d,18,8,18,11" name="mh2" origName="mh2">
60      <var fl="d18" loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" pinIndex="1" vartype="integer" origName="x_inout_wire_integer"/>
61    </module>
62    <module fl="d24" loc="d,24,8,24,11" name="mh5" origName="mh5">
63      <var fl="d24" loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_wire_logic"/>
64    </module>
65    <module fl="d26" loc="d,26,8,26,11" name="mh6" origName="mh6">
66      <var fl="d26" loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_var_logic"/>
67    </module>
68    <module fl="d28" loc="d,28,8,28,11" name="mh7" origName="mh7">
69      <var fl="d28" loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/>
70    </module>
71    <module fl="d30" loc="d,30,8,30,11" name="mh8" origName="mh8">
72      <var fl="d30" loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic"/>
73    </module>
74    <module fl="d32" loc="d,32,8,32,11" name="mh9" origName="mh9">
75      <var fl="d32" loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/>
76    </module>
77    <module fl="d34" loc="d,34,8,34,12" name="mh10" origName="mh10">
78      <var fl="d34" loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
79    </module>
80    <module fl="d36" loc="d,36,8,36,12" name="mh11" origName="mh11">
81      <var fl="d36" loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" pinIndex="1" vartype="integer" origName="x_output_var_integer"/>
82    </module>
83    <module fl="d38" loc="d,38,8,38,12" name="mh12" origName="mh12">
84      <var fl="d38" loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_logic_p6"/>
85    </module>
86    <module fl="d40" loc="d,40,8,40,12" name="mh13" origName="mh13">
87      <var fl="d40" loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" pinIndex="1" vartype="port" origName="x_ref_var_logic_u6"/>
88    </module>
89    <module fl="d50" loc="d,50,8,50,12" name="mh17" origName="mh17">
90      <var fl="d50" loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/>
91      <var fl="d50" loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/>
92    </module>
93    <module fl="d52" loc="d,52,8,52,12" name="mh18" origName="mh18">
94      <var fl="d52" loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/>
95      <var fl="d52" loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/>
96    </module>
97    <module fl="d54" loc="d,54,8,54,12" name="mh19" origName="mh19">
98      <var fl="d54" loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
99      <var fl="d54" loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" pinIndex="2" vartype="integer" origName="y_output_var_integer"/>
100    </module>
101    <module fl="d56" loc="d,56,8,56,12" name="mh20" origName="mh20">
102      <var fl="d56" loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_var_logic_p6"/>
103      <var fl="d56" loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic_p6"/>
104    </module>
105    <module fl="d58" loc="d,58,8,58,12" name="mh21" origName="mh21">
106      <var fl="d58" loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" pinIndex="1" vartype="port" origName="ref_var_logic_u6"/>
107      <var fl="d58" loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic"/>
108    </module>
109    <typetable fl="a0" loc="a,0,0,0,0">
110      <unpackarraydtype fl="d58" loc="d,58,34,58,35" id="6" sub_dtype_id="2">
111        <range fl="d58" loc="d,58,34,58,35">
112          <const fl="d58" loc="d,58,35,58,36" name="32&apos;sh5" dtype_id="7"/>
113          <const fl="d58" loc="d,58,37,58,38" name="32&apos;sh0" dtype_id="7"/>
114        </range>
115      </unpackarraydtype>
116      <basicdtype fl="d58" loc="d,58,41,58,56" id="2" name="logic"/>
117      <unpackarraydtype fl="d40" loc="d,40,36,40,37" id="5" sub_dtype_id="2">
118        <range fl="d40" loc="d,40,36,40,37">
119          <const fl="d40" loc="d,40,37,40,38" name="32&apos;sh5" dtype_id="7"/>
120          <const fl="d40" loc="d,40,39,40,40" name="32&apos;sh0" dtype_id="7"/>
121        </range>
122      </unpackarraydtype>
123      <basicdtype fl="d38" loc="d,38,17,38,18" id="4" name="logic" left="5" right="0"/>
124      <basicdtype fl="d34" loc="d,34,27,34,28" id="3" name="logic" left="5" right="0" signed="true"/>
125      <basicdtype fl="d18" loc="d,18,19,18,26" id="1" name="integer" left="31" right="0" signed="true"/>
126      <basicdtype fl="d40" loc="d,40,37,40,38" id="7" name="logic" left="31" right="0" signed="true"/>
127    </typetable>
128  </netlist>
129</verilator_xml>
130