1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2010 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7`verilator_config
8
9lint_off -rule DEPRECATED     -file "t/t_vlt_warn.vlt" -lines 14
10lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v"
11lint_off -rule WIDTH          -file "t/t_vlt_warn.v" -lines 19
12lint_off -rule DECLFILENAME   -file "*/t_vlt_warn.v"
13// Test wildcard filenames
14lint_off -msg WIDTH           -file "*/t_vlt_warn.v" -lines 20-20
15// Test global disables
16lint_off                      -file "*/t_vlt_warn.v" -lines 21-21
17// Test match
18lint_off -rule UNUSED         -file "*/t_vlt_warn.v" -match "Signal is not used: 'width_warn*'"
19
20coverage_off -file "t/t_vlt_warn.v"
21// Test --flag is also accepted
22tracing_off --file "t/t_vlt_warn.v"
23