1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2021 Wilson Snyder and Marlon James.
5// SPDX-License-Identifier: CC0-1.0
6
7
8module t (/*AUTOARG*/
9   // Inputs
10   clk
11   );
12
13   input clk;
14   int   count;
15
16   always @(posedge clk) begin
17      count <= count + 1;
18      if (count == 10) begin
19        $write("*-* All Finished *-*\n");
20        $finish;
21      end
22   end
23
24endmodule : t
25