1 /*
2  *  yosys -- Yosys Open SYnthesis Suite
3  *
4  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
5  *
6  *  Permission to use, copy, modify, and/or distribute this software for any
7  *  purpose with or without fee is hereby granted, provided that the above
8  *  copyright notice and this permission notice appear in all copies.
9  *
10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  *
18  */
19 
20 #ifndef CELLTYPES_H
21 #define CELLTYPES_H
22 
23 #include "kernel/yosys.h"
24 
25 YOSYS_NAMESPACE_BEGIN
26 
27 struct CellType
28 {
29 	RTLIL::IdString type;
30 	pool<RTLIL::IdString> inputs, outputs;
31 	bool is_evaluable;
32 };
33 
34 struct CellTypes
35 {
36 	dict<RTLIL::IdString, CellType> cell_types;
37 
CellTypesCellTypes38 	CellTypes()
39 	{
40 	}
41 
CellTypesCellTypes42 	CellTypes(RTLIL::Design *design)
43 	{
44 		setup(design);
45 	}
46 
47 	void setup(RTLIL::Design *design = NULL)
48 	{
49 		if (design)
50 			setup_design(design);
51 
52 		setup_internals();
53 		setup_internals_mem();
54 		setup_stdcells();
55 		setup_stdcells_mem();
56 	}
57 
58 	void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
59 	{
60 		CellType ct = {type, inputs, outputs, is_evaluable};
61 		cell_types[ct.type] = ct;
62 	}
63 
setup_moduleCellTypes64 	void setup_module(RTLIL::Module *module)
65 	{
66 		pool<RTLIL::IdString> inputs, outputs;
67 		for (RTLIL::IdString wire_name : module->ports) {
68 			RTLIL::Wire *wire = module->wire(wire_name);
69 			if (wire->port_input)
70 				inputs.insert(wire->name);
71 			if (wire->port_output)
72 				outputs.insert(wire->name);
73 		}
74 		setup_type(module->name, inputs, outputs);
75 	}
76 
setup_designCellTypes77 	void setup_design(RTLIL::Design *design)
78 	{
79 		for (auto module : design->modules())
80 			setup_module(module);
81 	}
82 
setup_internalsCellTypes83 	void setup_internals()
84 	{
85 		setup_internals_eval();
86 
87 		setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);
88 
89 		setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
90 		setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
91 		setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
92 		setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
93 		setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
94 		setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);
95 		setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);
96 		setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);
97 		setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);
98 		setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);
99 		setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);
100 		setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
101 		setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
102 		setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
103 	}
104 
setup_internals_evalCellTypes105 	void setup_internals_eval()
106 	{
107 		std::vector<RTLIL::IdString> unary_ops = {
108 			ID($not), ID($pos), ID($neg),
109 			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
110 			ID($logic_not), ID($slice), ID($lut), ID($sop)
111 		};
112 
113 		std::vector<RTLIL::IdString> binary_ops = {
114 			ID($and), ID($or), ID($xor), ID($xnor),
115 			ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
116 			ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
117 			ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
118 			ID($logic_and), ID($logic_or), ID($concat), ID($macc)
119 		};
120 
121 		for (auto type : unary_ops)
122 			setup_type(type, {ID::A}, {ID::Y}, true);
123 
124 		for (auto type : binary_ops)
125 			setup_type(type, {ID::A, ID::B}, {ID::Y}, true);
126 
127 		for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)}))
128 			setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);
129 
130 		setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
131 		setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
132 		setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
133 	}
134 
setup_internals_ffCellTypes135 	void setup_internals_ff()
136 	{
137 		setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});
138 		setup_type(ID($ff), {ID::D}, {ID::Q});
139 		setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
140 		setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
141 		setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
142 		setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});
143 		setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
144 		setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});
145 		setup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});
146 		setup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});
147 		setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});
148 		setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});
149 		setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});
150 		setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
151 		setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});
152 		setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
153 	}
154 
setup_internals_memCellTypes155 	void setup_internals_mem()
156 	{
157 		setup_internals_ff();
158 
159 		setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});
160 		setup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});
161 		setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
162 		setup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
163 		setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
164 		setup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());
165 		setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
166 		setup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
167 
168 		setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});
169 	}
170 
setup_stdcellsCellTypes171 	void setup_stdcells()
172 	{
173 		setup_stdcells_eval();
174 
175 		setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);
176 	}
177 
setup_stdcells_evalCellTypes178 	void setup_stdcells_eval()
179 	{
180 		setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);
181 		setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);
182 		setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);
183 		setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);
184 		setup_type(ID($_OR_),  {ID::A, ID::B}, {ID::Y}, true);
185 		setup_type(ID($_NOR_),  {ID::A, ID::B}, {ID::Y}, true);
186 		setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);
187 		setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);
188 		setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);
189 		setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);
190 		setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
191 		setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
192 		setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);
193 		setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);
194 		setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);
195 		setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
196 		setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
197 		setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
198 		setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
199 	}
200 
setup_stdcells_memCellTypes201 	void setup_stdcells_mem()
202 	{
203 		std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
204 
205 		for (auto c1 : list_np)
206 		for (auto c2 : list_np)
207 			setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q});
208 
209 		setup_type(ID($_FF_), {ID::D}, {ID::Q});
210 
211 		for (auto c1 : list_np)
212 			setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q});
213 
214 		for (auto c1 : list_np)
215 		for (auto c2 : list_np)
216 			setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});
217 
218 		for (auto c1 : list_np)
219 		for (auto c2 : list_np)
220 		for (auto c3 : list_01)
221 			setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
222 
223 		for (auto c1 : list_np)
224 		for (auto c2 : list_np)
225 		for (auto c3 : list_01)
226 		for (auto c4 : list_np)
227 			setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
228 
229 		for (auto c1 : list_np)
230 		for (auto c2 : list_np)
231 			setup_type(stringf("$_ALDFF_%c%c_", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});
232 
233 		for (auto c1 : list_np)
234 		for (auto c2 : list_np)
235 		for (auto c3 : list_np)
236 			setup_type(stringf("$_ALDFFE_%c%c%c_", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});
237 
238 		for (auto c1 : list_np)
239 		for (auto c2 : list_np)
240 		for (auto c3 : list_np)
241 			setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
242 
243 		for (auto c1 : list_np)
244 		for (auto c2 : list_np)
245 		for (auto c3 : list_np)
246 		for (auto c4 : list_np)
247 			setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});
248 
249 		for (auto c1 : list_np)
250 		for (auto c2 : list_np)
251 		for (auto c3 : list_01)
252 			setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
253 
254 		for (auto c1 : list_np)
255 		for (auto c2 : list_np)
256 		for (auto c3 : list_01)
257 		for (auto c4 : list_np)
258 			setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
259 
260 		for (auto c1 : list_np)
261 		for (auto c2 : list_np)
262 		for (auto c3 : list_01)
263 		for (auto c4 : list_np)
264 			setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
265 
266 		for (auto c1 : list_np)
267 			setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
268 
269 		for (auto c1 : list_np)
270 		for (auto c2 : list_np)
271 		for (auto c3 : list_01)
272 			setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});
273 
274 		for (auto c1 : list_np)
275 		for (auto c2 : list_np)
276 		for (auto c3 : list_np)
277 			setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
278 	}
279 
clearCellTypes280 	void clear()
281 	{
282 		cell_types.clear();
283 	}
284 
cell_knownCellTypes285 	bool cell_known(RTLIL::IdString type) const
286 	{
287 		return cell_types.count(type) != 0;
288 	}
289 
cell_outputCellTypes290 	bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
291 	{
292 		auto it = cell_types.find(type);
293 		return it != cell_types.end() && it->second.outputs.count(port) != 0;
294 	}
295 
cell_inputCellTypes296 	bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
297 	{
298 		auto it = cell_types.find(type);
299 		return it != cell_types.end() && it->second.inputs.count(port) != 0;
300 	}
301 
cell_evaluableCellTypes302 	bool cell_evaluable(RTLIL::IdString type) const
303 	{
304 		auto it = cell_types.find(type);
305 		return it != cell_types.end() && it->second.is_evaluable;
306 	}
307 
eval_notCellTypes308 	static RTLIL::Const eval_not(RTLIL::Const v)
309 	{
310 		for (auto &bit : v.bits)
311 			if (bit == State::S0) bit = State::S1;
312 			else if (bit == State::S1) bit = State::S0;
313 		return v;
314 	}
315 
316 	static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)
317 	{
318 		if (type == ID($sshr) && !signed1)
319 			type = ID($shr);
320 		if (type == ID($sshl) && !signed1)
321 			type = ID($shl);
322 
323 		if (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&
324 				type != ID($pos) && type != ID($neg) && type != ID($not)) {
325 			if (!signed1 || !signed2)
326 				signed1 = false, signed2 = false;
327 		}
328 
329 #define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
330 		HANDLE_CELL_TYPE(not)
331 		HANDLE_CELL_TYPE(and)
332 		HANDLE_CELL_TYPE(or)
333 		HANDLE_CELL_TYPE(xor)
334 		HANDLE_CELL_TYPE(xnor)
335 		HANDLE_CELL_TYPE(reduce_and)
336 		HANDLE_CELL_TYPE(reduce_or)
337 		HANDLE_CELL_TYPE(reduce_xor)
338 		HANDLE_CELL_TYPE(reduce_xnor)
339 		HANDLE_CELL_TYPE(reduce_bool)
340 		HANDLE_CELL_TYPE(logic_not)
341 		HANDLE_CELL_TYPE(logic_and)
342 		HANDLE_CELL_TYPE(logic_or)
343 		HANDLE_CELL_TYPE(shl)
344 		HANDLE_CELL_TYPE(shr)
345 		HANDLE_CELL_TYPE(sshl)
346 		HANDLE_CELL_TYPE(sshr)
347 		HANDLE_CELL_TYPE(shift)
348 		HANDLE_CELL_TYPE(shiftx)
349 		HANDLE_CELL_TYPE(lt)
350 		HANDLE_CELL_TYPE(le)
351 		HANDLE_CELL_TYPE(eq)
352 		HANDLE_CELL_TYPE(ne)
353 		HANDLE_CELL_TYPE(eqx)
354 		HANDLE_CELL_TYPE(nex)
355 		HANDLE_CELL_TYPE(ge)
356 		HANDLE_CELL_TYPE(gt)
357 		HANDLE_CELL_TYPE(add)
358 		HANDLE_CELL_TYPE(sub)
359 		HANDLE_CELL_TYPE(mul)
360 		HANDLE_CELL_TYPE(div)
361 		HANDLE_CELL_TYPE(mod)
362 		HANDLE_CELL_TYPE(divfloor)
363 		HANDLE_CELL_TYPE(modfloor)
364 		HANDLE_CELL_TYPE(pow)
365 		HANDLE_CELL_TYPE(pos)
366 		HANDLE_CELL_TYPE(neg)
367 #undef HANDLE_CELL_TYPE
368 
369 		if (type == ID($_BUF_))
370 			return arg1;
371 		if (type == ID($_NOT_))
372 			return eval_not(arg1);
373 		if (type == ID($_AND_))
374 			return const_and(arg1, arg2, false, false, 1);
375 		if (type == ID($_NAND_))
376 			return eval_not(const_and(arg1, arg2, false, false, 1));
377 		if (type == ID($_OR_))
378 			return const_or(arg1, arg2, false, false, 1);
379 		if (type == ID($_NOR_))
380 			return eval_not(const_or(arg1, arg2, false, false, 1));
381 		if (type == ID($_XOR_))
382 			return const_xor(arg1, arg2, false, false, 1);
383 		if (type == ID($_XNOR_))
384 			return const_xnor(arg1, arg2, false, false, 1);
385 		if (type == ID($_ANDNOT_))
386 			return const_and(arg1, eval_not(arg2), false, false, 1);
387 		if (type == ID($_ORNOT_))
388 			return const_or(arg1, eval_not(arg2), false, false, 1);
389 
390 		if (errp != nullptr) {
391 			*errp = true;
392 			return State::Sm;
393 		}
394 
395 		log_abort();
396 	}
397 
398 	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
399 	{
400 		if (cell->type == ID($slice)) {
401 			RTLIL::Const ret;
402 			int width = cell->parameters.at(ID::Y_WIDTH).as_int();
403 			int offset = cell->parameters.at(ID::OFFSET).as_int();
404 			ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
405 			return ret;
406 		}
407 
408 		if (cell->type == ID($concat)) {
409 			RTLIL::Const ret = arg1;
410 			ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
411 			return ret;
412 		}
413 
414 		if (cell->type == ID($lut))
415 		{
416 			int width = cell->parameters.at(ID::WIDTH).as_int();
417 
418 			std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
419 			while (GetSize(t) < (1 << width))
420 				t.push_back(State::S0);
421 			t.resize(1 << width);
422 
423 			for (int i = width-1; i >= 0; i--) {
424 				RTLIL::State sel = arg1.bits.at(i);
425 				std::vector<RTLIL::State> new_t;
426 				if (sel == State::S0)
427 					new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
428 				else if (sel == State::S1)
429 					new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
430 				else
431 					for (int j = 0; j < GetSize(t)/2; j++)
432 						new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
433 				t.swap(new_t);
434 			}
435 
436 			log_assert(GetSize(t) == 1);
437 			return t;
438 		}
439 
440 		if (cell->type == ID($sop))
441 		{
442 			int width = cell->parameters.at(ID::WIDTH).as_int();
443 			int depth = cell->parameters.at(ID::DEPTH).as_int();
444 			std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
445 
446 			while (GetSize(t) < width*depth*2)
447 				t.push_back(State::S0);
448 
449 			RTLIL::State default_ret = State::S0;
450 
451 			for (int i = 0; i < depth; i++)
452 			{
453 				bool match = true;
454 				bool match_x = true;
455 
456 				for (int j = 0; j < width; j++) {
457 					RTLIL::State a = arg1.bits.at(j);
458 					if (t.at(2*width*i + 2*j + 0) == State::S1) {
459 						if (a == State::S1) match_x = false;
460 						if (a != State::S0) match = false;
461 					}
462 					if (t.at(2*width*i + 2*j + 1) == State::S1) {
463 						if (a == State::S0) match_x = false;
464 						if (a != State::S1) match = false;
465 					}
466 				}
467 
468 				if (match)
469 					return State::S1;
470 
471 				if (match_x)
472 					default_ret = State::Sx;
473 			}
474 
475 			return default_ret;
476 		}
477 
478 		bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
479 		bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
480 		int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;
481 		return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
482 	}
483 
484 	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)
485 	{
486 		if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
487 			RTLIL::Const ret = arg1;
488 			for (size_t i = 0; i < arg3.bits.size(); i++)
489 				if (arg3.bits[i] == RTLIL::State::S1) {
490 					std::vector<RTLIL::State> bits(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size());
491 					ret = RTLIL::Const(bits);
492 				}
493 			return ret;
494 		}
495 
496 		if (cell->type == ID($_AOI3_))
497 			return eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));
498 		if (cell->type == ID($_OAI3_))
499 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
500 
501 		log_assert(arg3.bits.size() == 0);
502 		return eval(cell, arg1, arg2, errp);
503 	}
504 
505 	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)
506 	{
507 		if (cell->type == ID($_AOI4_))
508 			return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
509 		if (cell->type == ID($_OAI4_))
510 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
511 
512 		log_assert(arg4.bits.size() == 0);
513 		return eval(cell, arg1, arg2, arg3, errp);
514 	}
515 };
516 
517 // initialized by yosys_setup()
518 extern CellTypes yosys_celltypes;
519 
520 YOSYS_NAMESPACE_END
521 
522 #endif
523