1 /* 2 * yosys -- Yosys Open SYnthesis Suite 3 * 4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 */ 19 20 #include "kernel/yosys.h" 21 #include "kernel/sigtools.h" 22 #include "kernel/modtools.h" 23 #include "kernel/ffinit.h" 24 25 USING_YOSYS_NAMESPACE 26 27 PRIVATE_NAMESPACE_BEGIN 28 29 struct WreduceConfig 30 { 31 pool<IdString> supported_cell_types; 32 bool keepdc = false; 33 WreduceConfigWreduceConfig34 WreduceConfig() 35 { 36 supported_cell_types = pool<IdString>({ 37 ID($not), ID($pos), ID($neg), 38 ID($and), ID($or), ID($xor), ID($xnor), 39 ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), 40 ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), 41 ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), 42 ID($mux), ID($pmux), 43 ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), 44 ID($dlatch), ID($adlatch), 45 }); 46 } 47 }; 48 49 struct WreduceWorker 50 { 51 WreduceConfig *config; 52 Module *module; 53 ModIndex mi; 54 55 std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells; 56 std::set<SigBit> work_queue_bits; 57 pool<SigBit> keep_bits; 58 FfInitVals initvals; 59 WreduceWorkerWreduceWorker60 WreduceWorker(WreduceConfig *config, Module *module) : 61 config(config), module(module), mi(module) { } 62 run_cell_muxWreduceWorker63 void run_cell_mux(Cell *cell) 64 { 65 // Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused 66 67 SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)); 68 SigSpec sig_b = mi.sigmap(cell->getPort(ID::B)); 69 SigSpec sig_s = mi.sigmap(cell->getPort(ID::S)); 70 SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y)); 71 std::vector<SigBit> bits_removed; 72 73 if (sig_y.has_const()) 74 return; 75 76 for (int i = GetSize(sig_y)-1; i >= 0; i--) 77 { 78 auto info = mi.query(sig_y[i]); 79 if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_y[i]))) { 80 bits_removed.push_back(State::Sx); 81 continue; 82 } 83 84 SigBit ref = sig_a[i]; 85 for (int k = 0; k < GetSize(sig_s); k++) { 86 if ((config->keepdc || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k*GetSize(sig_a) + i]) 87 goto no_match_ab; 88 if (sig_b[k*GetSize(sig_a) + i] != State::Sx) 89 ref = sig_b[k*GetSize(sig_a) + i]; 90 } 91 if (0) 92 no_match_ab: 93 break; 94 bits_removed.push_back(ref); 95 } 96 97 if (bits_removed.empty()) 98 return; 99 100 SigSpec sig_removed; 101 for (int i = GetSize(bits_removed)-1; i >= 0; i--) 102 sig_removed.append(bits_removed[i]); 103 104 if (GetSize(bits_removed) == GetSize(sig_y)) { 105 log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); 106 module->connect(sig_y, sig_removed); 107 module->remove(cell); 108 return; 109 } 110 111 log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", 112 GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type)); 113 114 int n_removed = GetSize(sig_removed); 115 int n_kept = GetSize(sig_y) - GetSize(sig_removed); 116 117 SigSpec new_work_queue_bits; 118 new_work_queue_bits.append(sig_a.extract(n_kept, n_removed)); 119 new_work_queue_bits.append(sig_y.extract(n_kept, n_removed)); 120 121 SigSpec new_sig_a = sig_a.extract(0, n_kept); 122 SigSpec new_sig_y = sig_y.extract(0, n_kept); 123 SigSpec new_sig_b; 124 125 for (int k = 0; k < GetSize(sig_s); k++) { 126 new_sig_b.append(sig_b.extract(k*GetSize(sig_a), n_kept)); 127 new_work_queue_bits.append(sig_b.extract(k*GetSize(sig_a) + n_kept, n_removed)); 128 } 129 130 for (auto bit : new_work_queue_bits) 131 work_queue_bits.insert(bit); 132 133 cell->setPort(ID::A, new_sig_a); 134 cell->setPort(ID::B, new_sig_b); 135 cell->setPort(ID::Y, new_sig_y); 136 cell->fixup_parameters(); 137 138 module->connect(sig_y.extract(n_kept, n_removed), sig_removed); 139 } 140 run_cell_dffWreduceWorker141 void run_cell_dff(Cell *cell) 142 { 143 // Reduce size of FF if inputs are just sign/zero extended or output bit is not used 144 145 SigSpec sig_d = mi.sigmap(cell->getPort(ID::D)); 146 SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q)); 147 bool has_reset = false; 148 Const initval = initvals(sig_q), rst_value; 149 150 int width_before = GetSize(sig_q); 151 152 if (width_before == 0) 153 return; 154 155 if (cell->parameters.count(ID::ARST_VALUE)) { 156 rst_value = cell->parameters[ID::ARST_VALUE]; 157 has_reset = true; 158 } else if (cell->parameters.count(ID::SRST_VALUE)) { 159 rst_value = cell->parameters[ID::SRST_VALUE]; 160 has_reset = true; 161 } 162 163 bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0; 164 bool sign_ext = !zero_ext; 165 166 for (int i = GetSize(sig_q)-1; i >= 0; i--) 167 { 168 if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) && 169 (!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx)) { 170 module->connect(sig_q[i], State::S0); 171 initvals.remove_init(sig_q[i]); 172 sig_d.remove(i); 173 sig_q.remove(i); 174 continue; 175 } 176 177 if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] && 178 (!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) { 179 module->connect(sig_q[i], sig_q[i-1]); 180 initvals.remove_init(sig_q[i]); 181 sig_d.remove(i); 182 sig_q.remove(i); 183 continue; 184 } 185 186 auto info = mi.query(sig_q[i]); 187 if (info == nullptr) 188 return; 189 if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) { 190 initvals.remove_init(sig_q[i]); 191 sig_d.remove(i); 192 sig_q.remove(i); 193 zero_ext = false; 194 sign_ext = false; 195 continue; 196 } 197 198 break; 199 } 200 201 if (width_before == GetSize(sig_q)) 202 return; 203 204 if (GetSize(sig_q) == 0) { 205 log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); 206 module->remove(cell); 207 return; 208 } 209 210 log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before, 211 log_id(module), log_id(cell), log_id(cell->type)); 212 213 for (auto bit : sig_d) 214 work_queue_bits.insert(bit); 215 216 for (auto bit : sig_q) 217 work_queue_bits.insert(bit); 218 219 // Narrow ARST_VALUE parameter to new size. 220 if (cell->parameters.count(ID::ARST_VALUE)) { 221 rst_value.bits.resize(GetSize(sig_q)); 222 cell->setParam(ID::ARST_VALUE, rst_value); 223 } else if (cell->parameters.count(ID::SRST_VALUE)) { 224 rst_value.bits.resize(GetSize(sig_q)); 225 cell->setParam(ID::SRST_VALUE, rst_value); 226 } 227 228 cell->setPort(ID::D, sig_d); 229 cell->setPort(ID::Q, sig_q); 230 cell->fixup_parameters(); 231 } 232 run_reduce_inportWreduceWorker233 void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something) 234 { 235 port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); 236 SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port))); 237 238 if (port == 'B' && cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) 239 port_signed = false; 240 241 int bits_removed = 0; 242 if (GetSize(sig) > max_port_size) { 243 bits_removed = GetSize(sig) - max_port_size; 244 for (auto bit : sig.extract(max_port_size, bits_removed)) 245 work_queue_bits.insert(bit); 246 sig = sig.extract(0, max_port_size); 247 } 248 249 if (port_signed) { 250 while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == sig[GetSize(sig)-2]) 251 work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++; 252 } else { 253 while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == State::S0) 254 work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++; 255 } 256 257 if (bits_removed) { 258 log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", 259 bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); 260 cell->setPort(stringf("\\%c", port), sig); 261 did_something = true; 262 } 263 } 264 run_cellWreduceWorker265 void run_cell(Cell *cell) 266 { 267 bool did_something = false; 268 269 if (!cell->type.in(config->supported_cell_types)) 270 return; 271 272 if (cell->type.in(ID($mux), ID($pmux))) 273 return run_cell_mux(cell); 274 275 if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch))) 276 return run_cell_dff(cell); 277 278 SigSpec sig = mi.sigmap(cell->getPort(ID::Y)); 279 280 if (sig.has_const()) 281 return; 282 283 284 // Reduce size of ports A and B based on constant input bits and size of output port 285 286 int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : -1; 287 int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : -1; 288 289 if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) { 290 max_port_a_size = min(max_port_a_size, GetSize(sig)); 291 max_port_b_size = min(max_port_b_size, GetSize(sig)); 292 } 293 294 bool port_a_signed = false; 295 bool port_b_signed = false; 296 297 if (max_port_a_size >= 0 && cell->type != ID($shiftx)) 298 run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something); 299 300 if (max_port_b_size >= 0) 301 run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something); 302 303 if (cell->hasPort(ID::A) && cell->hasPort(ID::B) && port_a_signed && port_b_signed) { 304 SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B)); 305 if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 && 306 GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) { 307 log("Converting cell %s.%s (%s) from signed to unsigned.\n", 308 log_id(module), log_id(cell), log_id(cell->type)); 309 cell->setParam(ID::A_SIGNED, 0); 310 cell->setParam(ID::B_SIGNED, 0); 311 port_a_signed = false; 312 port_b_signed = false; 313 did_something = true; 314 } 315 } 316 317 if (cell->hasPort(ID::A) && !cell->hasPort(ID::B) && port_a_signed) { 318 SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)); 319 if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) { 320 log("Converting cell %s.%s (%s) from signed to unsigned.\n", 321 log_id(module), log_id(cell), log_id(cell->type)); 322 cell->setParam(ID::A_SIGNED, 0); 323 port_a_signed = false; 324 did_something = true; 325 } 326 } 327 328 329 // Reduce size of port Y based on sizes for A and B and unused bits in Y 330 331 int bits_removed = 0; 332 if (port_a_signed && cell->type == ID($shr)) { 333 // do not reduce size of output on $shr cells with signed A inputs 334 } else { 335 while (GetSize(sig) > 0) 336 { 337 auto bit = sig[GetSize(sig)-1]; 338 if (keep_bits.count(bit)) 339 break; 340 341 auto info = mi.query(bit); 342 if (info->is_output || GetSize(info->ports) > 1) 343 break; 344 345 sig.remove(GetSize(sig)-1); 346 bits_removed++; 347 } 348 } 349 350 if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub))) 351 { 352 bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub); 353 354 int a_size = 0, b_size = 0; 355 if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A)); 356 if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(ID::B)); 357 358 int max_y_size = max(a_size, b_size); 359 360 if (cell->type.in(ID($add), ID($sub))) 361 max_y_size++; 362 363 if (cell->type == ID($mul)) 364 max_y_size = a_size + b_size; 365 366 while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) { 367 module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : State::S0); 368 sig.remove(GetSize(sig)-1); 369 bits_removed++; 370 } 371 } 372 373 if (GetSize(sig) == 0) { 374 log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); 375 module->remove(cell); 376 return; 377 } 378 379 if (bits_removed) { 380 log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", 381 bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); 382 cell->setPort(ID::Y, sig); 383 did_something = true; 384 } 385 386 if (did_something) { 387 cell->fixup_parameters(); 388 run_cell(cell); 389 } 390 } 391 count_nontrivial_wire_attrsWreduceWorker392 static int count_nontrivial_wire_attrs(RTLIL::Wire *w) 393 { 394 int count = w->attributes.size(); 395 count -= w->attributes.count(ID::src); 396 count -= w->attributes.count(ID::unused_bits); 397 return count; 398 } 399 runWreduceWorker400 void run() 401 { 402 // create a copy as mi.sigmap will be updated as we process the module 403 SigMap init_attr_sigmap = mi.sigmap; 404 initvals.set(&init_attr_sigmap, module); 405 406 for (auto w : module->wires()) { 407 if (w->get_bool_attribute(ID::keep)) 408 for (auto bit : mi.sigmap(w)) 409 keep_bits.insert(bit); 410 } 411 412 for (auto c : module->selected_cells()) 413 work_queue_cells.insert(c); 414 415 while (!work_queue_cells.empty()) 416 { 417 work_queue_bits.clear(); 418 for (auto c : work_queue_cells) 419 run_cell(c); 420 421 work_queue_cells.clear(); 422 for (auto bit : work_queue_bits) 423 for (auto port : mi.query_ports(bit)) 424 if (module->selected(port.cell)) 425 work_queue_cells.insert(port.cell); 426 } 427 428 pool<SigSpec> complete_wires; 429 for (auto w : module->wires()) 430 complete_wires.insert(mi.sigmap(w)); 431 432 for (auto w : module->selected_wires()) 433 { 434 int unused_top_bits = 0; 435 436 if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0) 437 continue; 438 439 for (int i = GetSize(w)-1; i >= 0; i--) { 440 SigBit bit(w, i); 441 auto info = mi.query(bit); 442 if (info && (info->is_input || info->is_output || GetSize(info->ports) > 0)) 443 break; 444 unused_top_bits++; 445 } 446 447 if (unused_top_bits == 0 || unused_top_bits == GetSize(w)) 448 continue; 449 450 if (complete_wires[mi.sigmap(w).extract(0, GetSize(w) - unused_top_bits)]) 451 continue; 452 453 log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); 454 Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits); 455 module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); 456 module->swap_names(w, nw); 457 } 458 } 459 }; 460 461 struct WreducePass : public Pass { WreducePassWreducePass462 WreducePass() : Pass("wreduce", "reduce the word size of operations if possible") { } helpWreducePass463 void help() override 464 { 465 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| 466 log("\n"); 467 log(" wreduce [options] [selection]\n"); 468 log("\n"); 469 log("This command reduces the word size of operations. For example it will replace\n"); 470 log("the 32 bit adders in the following code with adders of more appropriate widths:\n"); 471 log("\n"); 472 log(" module test(input [3:0] a, b, c, output [7:0] y);\n"); 473 log(" assign y = a + b + c + 1;\n"); 474 log(" endmodule\n"); 475 log("\n"); 476 log("Options:\n"); 477 log("\n"); 478 log(" -memx\n"); 479 log(" Do not change the width of memory address ports. Use this options in\n"); 480 log(" flows that use the 'memory_memx' pass.\n"); 481 log("\n"); 482 log(" -keepdc\n"); 483 log(" Do not optimize explicit don't-care values.\n"); 484 log("\n"); 485 } executeWreducePass486 void execute(std::vector<std::string> args, Design *design) override 487 { 488 WreduceConfig config; 489 bool opt_memx = false; 490 491 log_header(design, "Executing WREDUCE pass (reducing word size of cells).\n"); 492 493 size_t argidx; 494 for (argidx = 1; argidx < args.size(); argidx++) { 495 if (args[argidx] == "-memx") { 496 opt_memx = true; 497 continue; 498 } 499 if (args[argidx] == "-keepdc") { 500 config.keepdc = true; 501 continue; 502 } 503 break; 504 } 505 extra_args(args, argidx, design); 506 507 for (auto module : design->selected_modules()) 508 { 509 if (module->has_processes_warn()) 510 continue; 511 512 for (auto c : module->selected_cells()) 513 { 514 if (c->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), 515 ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), 516 ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(ID::Y)) > 1) { 517 SigSpec sig = c->getPort(ID::Y); 518 if (!sig.has_const()) { 519 c->setPort(ID::Y, sig[0]); 520 c->setParam(ID::Y_WIDTH, 1); 521 sig.remove(0); 522 module->connect(sig, Const(0, GetSize(sig))); 523 } 524 } 525 526 if (c->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) 527 { 528 SigSpec A = c->getPort(ID::A); 529 int original_a_width = GetSize(A); 530 if (c->getParam(ID::A_SIGNED).as_bool()) { 531 while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0) 532 A.remove(GetSize(A)-1, 1); 533 } else { 534 while (GetSize(A) > 0 && A[GetSize(A)-1] == State::S0) 535 A.remove(GetSize(A)-1, 1); 536 } 537 if (original_a_width != GetSize(A)) { 538 log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n", 539 original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type)); 540 c->setPort(ID::A, A); 541 c->setParam(ID::A_WIDTH, GetSize(A)); 542 } 543 544 SigSpec B = c->getPort(ID::B); 545 int original_b_width = GetSize(B); 546 if (c->getParam(ID::B_SIGNED).as_bool()) { 547 while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0) 548 B.remove(GetSize(B)-1, 1); 549 } else { 550 while (GetSize(B) > 0 && B[GetSize(B)-1] == State::S0) 551 B.remove(GetSize(B)-1, 1); 552 } 553 if (original_b_width != GetSize(B)) { 554 log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n", 555 original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type)); 556 c->setPort(ID::B, B); 557 c->setParam(ID::B_WIDTH, GetSize(B)); 558 } 559 } 560 561 if (!opt_memx && c->type.in(ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) { 562 IdString memid = c->getParam(ID::MEMID).decode_string(); 563 RTLIL::Memory *mem = module->memories.at(memid); 564 if (mem->start_offset >= 0) { 565 int cur_addrbits = c->getParam(ID::ABITS).as_int(); 566 int max_addrbits = ceil_log2(mem->start_offset + mem->size); 567 if (cur_addrbits > max_addrbits) { 568 log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n", 569 cur_addrbits-max_addrbits, cur_addrbits, 570 c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init", 571 log_id(module), log_id(c), log_id(memid)); 572 c->setParam(ID::ABITS, max_addrbits); 573 c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits)); 574 } 575 } 576 } 577 } 578 579 WreduceWorker worker(&config, module); 580 worker.run(); 581 } 582 } 583 } WreducePass; 584 585 PRIVATE_NAMESPACE_END 586 587