1// ECP5 Blackbox cells
2// FIXME: Create sim models
3
4(* blackbox *)
5module MULT18X18D(
6	input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,
7	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,
8	input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,
9	input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,
10	input CLK0, CLK1, CLK2, CLK3,
11	input CE0, CE1, CE2, CE3,
12	input RST0, RST1, RST2, RST3,
13	input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,
14	input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,
15	output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,
16	output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,
17	output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,
18	output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,
19	output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,
20	output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,
21	output SIGNEDP
22);
23	parameter REG_INPUTA_CLK = "NONE";
24	parameter REG_INPUTA_CE = "CE0";
25	parameter REG_INPUTA_RST = "RST0";
26	parameter REG_INPUTB_CLK = "NONE";
27	parameter REG_INPUTB_CE = "CE0";
28	parameter REG_INPUTB_RST = "RST0";
29	parameter REG_INPUTC_CLK = "NONE";
30	parameter REG_INPUTC_CE = "CE0";
31	parameter REG_INPUTC_RST = "RST0";
32	parameter REG_PIPELINE_CLK = "NONE";
33	parameter REG_PIPELINE_CE = "CE0";
34	parameter REG_PIPELINE_RST = "RST0";
35	parameter REG_OUTPUT_CLK = "NONE";
36	parameter REG_OUTPUT_CE = "CE0";
37	parameter REG_OUTPUT_RST = "RST0";
38	parameter [127:0] CLK0_DIV = "ENABLED";
39	parameter [127:0] CLK1_DIV = "ENABLED";
40	parameter [127:0] CLK2_DIV = "ENABLED";
41	parameter [127:0] CLK3_DIV = "ENABLED";
42	parameter HIGHSPEED_CLK = "NONE";
43	parameter [127:0] GSR = "ENABLED";
44	parameter CAS_MATCH_REG = "FALSE";
45	parameter [127:0] SOURCEB_MODE = "B_SHIFT";
46	parameter [127:0] MULT_BYPASS = "DISABLED";
47	parameter [127:0] RESETMODE = "SYNC";
48endmodule
49
50(* blackbox *)
51module ALU54B(
52	input CLK0, CLK1, CLK2, CLK3,
53	input CE0, CE1, CE2, CE3,
54	input RST0, RST1, RST2, RST3,
55	input SIGNEDIA, SIGNEDIB, SIGNEDCIN,
56	input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35,
57	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35,
58	input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53,
59	input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53,
60	input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35,
61	input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35,
62	input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53,
63	input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10,
64	output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53,
65	output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53,
66	output EQZ, EQZM, EQOM, EQPAT, EQPATB,
67	output OVER, UNDER, OVERUNDER,
68	output SIGNEDR
69);
70	parameter REG_INPUTC0_CLK = "NONE";
71	parameter REG_INPUTC0_CE = "CE0";
72	parameter REG_INPUTC0_RST = "RST0";
73	parameter REG_INPUTC1_CLK = "NONE";
74	parameter REG_INPUTC1_CE = "CE0";
75	parameter REG_INPUTC1_RST = "RST0";
76	parameter REG_OPCODEOP0_0_CLK = "NONE";
77	parameter REG_OPCODEOP0_0_CE = "CE0";
78	parameter REG_OPCODEOP0_0_RST = "RST0";
79	parameter REG_OPCODEOP1_0_CLK = "NONE";
80	parameter REG_OPCODEOP0_1_CLK = "NONE";
81	parameter REG_OPCODEOP0_1_CE = "CE0";
82	parameter REG_OPCODEOP0_1_RST = "RST0";
83	parameter REG_OPCODEOP1_1_CLK = "NONE";
84	parameter REG_OPCODEIN_0_CLK = "NONE";
85	parameter REG_OPCODEIN_0_CE = "CE0";
86	parameter REG_OPCODEIN_0_RST = "RST0";
87	parameter REG_OPCODEIN_1_CLK = "NONE";
88	parameter REG_OPCODEIN_1_CE = "CE0";
89	parameter REG_OPCODEIN_1_RST = "RST0";
90	parameter REG_OUTPUT0_CLK = "NONE";
91	parameter REG_OUTPUT0_CE = "CE0";
92	parameter REG_OUTPUT0_RST = "RST0";
93	parameter REG_OUTPUT1_CLK = "NONE";
94	parameter REG_OUTPUT1_CE = "CE0";
95	parameter REG_OUTPUT1_RST = "RST0";
96	parameter REG_FLAG_CLK = "NONE";
97	parameter REG_FLAG_CE = "CE0";
98	parameter REG_FLAG_RST = "RST0";
99	parameter REG_INPUTCFB_CLK = "NONE";
100	parameter REG_INPUTCFB_CE = "CE0";
101	parameter REG_INPUTCFB_RST = "RST0";
102	parameter [127:0] MCPAT_SOURCE = "STATIC";
103	parameter [127:0] MASKPAT_SOURCE = "STATIC";
104	parameter MASK01 = "0x00000000000000";
105	parameter [127:0] CLK0_DIV = "ENABLED";
106	parameter [127:0] CLK1_DIV = "ENABLED";
107	parameter [127:0] CLK2_DIV = "ENABLED";
108	parameter [127:0] CLK3_DIV = "ENABLED";
109	parameter MCPAT = "0x00000000000000";
110	parameter MASKPAT = "0x00000000000000";
111	parameter RNDPAT = "0x00000000000000";
112	parameter [127:0] GSR = "ENABLED";
113	parameter [127:0] RESETMODE = "SYNC";
114	parameter MULT9_MODE = "DISABLED";
115	parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
116	parameter LEGACY = "DISABLED";
117endmodule
118
119(* blackbox *)
120module EHXPLLL (
121	input CLKI, CLKFB,
122	input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,
123	input STDBY, PLLWAKESYNC,
124	input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,
125	output CLKOP, CLKOS, CLKOS2, CLKOS3,
126	output LOCK, INTLOCK,
127	output REFCLK, CLKINTFB
128);
129	parameter CLKI_DIV = 1;
130	parameter CLKFB_DIV = 1;
131	parameter CLKOP_DIV = 8;
132	parameter CLKOS_DIV = 8;
133	parameter CLKOS2_DIV = 8;
134	parameter CLKOS3_DIV = 8;
135	parameter CLKOP_ENABLE = "ENABLED";
136	parameter CLKOS_ENABLE = "DISABLED";
137	parameter CLKOS2_ENABLE = "DISABLED";
138	parameter CLKOS3_ENABLE = "DISABLED";
139	parameter CLKOP_CPHASE = 0;
140	parameter CLKOS_CPHASE = 0;
141	parameter CLKOS2_CPHASE = 0;
142	parameter CLKOS3_CPHASE = 0;
143	parameter CLKOP_FPHASE = 0;
144	parameter CLKOS_FPHASE = 0;
145	parameter CLKOS2_FPHASE = 0;
146	parameter CLKOS3_FPHASE = 0;
147	parameter FEEDBK_PATH = "CLKOP";
148	parameter CLKOP_TRIM_POL = "RISING";
149	parameter CLKOP_TRIM_DELAY = 0;
150	parameter CLKOS_TRIM_POL = "RISING";
151	parameter CLKOS_TRIM_DELAY = 0;
152	parameter OUTDIVIDER_MUXA = "DIVA";
153	parameter OUTDIVIDER_MUXB = "DIVB";
154	parameter OUTDIVIDER_MUXC = "DIVC";
155	parameter OUTDIVIDER_MUXD = "DIVD";
156	parameter PLL_LOCK_MODE = 0;
157	parameter PLL_LOCK_DELAY = 200;
158	parameter STDBY_ENABLE = "DISABLED";
159	parameter REFIN_RESET = "DISABLED";
160	parameter SYNC_ENABLE = "DISABLED";
161	parameter INT_LOCK_STICKY = "ENABLED";
162	parameter DPHASE_SOURCE = "DISABLED";
163	parameter PLLRST_ENA = "DISABLED";
164	parameter INTFB_WAKE = "DISABLED";
165endmodule
166
167(* blackbox *)
168module DTR(
169	input STARTPULSE,
170	output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0
171);
172endmodule
173
174(* blackbox *)
175module OSCG(
176	output OSC
177);
178parameter DIV = 128;
179endmodule
180
181(* blackbox *) (* keep *)
182module USRMCLK(
183	input USRMCLKI, USRMCLKTS,
184	output USRMCLKO
185);
186endmodule
187
188(* blackbox *) (* keep *)
189module JTAGG(
190	input TCK, TMS, TDI, JTDO2, JTDO1,
191	output TDO, JTDI, JTCK, JRTI2, JRTI1,
192	output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1
193);
194parameter ER1 = "ENABLED";
195parameter ER2 = "ENABLED";
196endmodule
197
198(* blackbox *)
199module DELAYF(
200	input A, LOADN, MOVE, DIRECTION,
201	output Z, CFLAG
202);
203	parameter DEL_MODE = "USER_DEFINED";
204	parameter DEL_VALUE = 0;
205endmodule
206
207(* blackbox *)
208module DELAYG(
209	input A,
210	output Z
211);
212	parameter DEL_MODE = "USER_DEFINED";
213	parameter DEL_VALUE = 0;
214endmodule
215
216(* blackbox *)
217module IDDRX1F(
218	input D, SCLK, RST,
219	output Q0, Q1
220);
221	parameter GSR = "ENABLED";
222endmodule
223
224(* blackbox *)
225module IDDRX2F(
226	input D, SCLK, ECLK, RST,
227	output Q0, Q1, Q2, Q3
228);
229	parameter GSR = "ENABLED";
230endmodule
231
232(* blackbox *)
233module IDDR71B(
234	input D, SCLK, ECLK, RST, ALIGNWD,
235	output Q0, Q1, Q2, Q3, Q4, Q5, Q6
236);
237	parameter GSR = "ENABLED";
238endmodule
239
240(* blackbox *)
241module IDDRX2DQA(
242	input D, DQSR90, ECLK, SCLK, RST,
243	input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
244	output Q0, Q1, Q2, Q3, QWL
245);
246	parameter GSR = "ENABLED";
247endmodule
248
249(* blackbox *)
250module ODDRX1F(
251	input SCLK, RST, D0, D1,
252	output Q
253);
254	parameter GSR = "ENABLED";
255endmodule
256
257(* blackbox *)
258module ODDRX2F(
259	input SCLK, ECLK, RST, D0, D1, D2, D3,
260	output Q
261);
262	parameter GSR = "ENABLED";
263endmodule
264
265(* blackbox *)
266module ODDR71B(
267	input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6,
268	output Q
269);
270	parameter GSR = "ENABLED";
271endmodule
272
273(* blackbox *)
274module OSHX2A(
275	input D0, D1, RST, ECLK, SCLK,
276	output Q
277);
278	parameter GSR = "ENABLED";
279endmodule
280
281(* blackbox *)
282module ODDRX2DQA(
283	input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270,
284	output Q
285);
286	parameter GSR = "ENABLED";
287endmodule
288
289(* blackbox *)
290module ODDRX2DQSB(
291	input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW,
292	output Q
293);
294	parameter GSR = "ENABLED";
295endmodule
296
297(* blackbox *)
298module TSHX2DQA(
299	input T0, T1, SCLK, ECLK, DQSW270, RST,
300	output Q
301);
302	parameter GSR = "ENABLED";
303	parameter REGSET = "SET";
304endmodule
305
306(* blackbox *)
307module TSHX2DQSA(
308	input T0, T1, SCLK, ECLK, DQSW, RST,
309	output Q
310);
311	parameter GSR = "ENABLED";
312	parameter REGSET = "SET";
313endmodule
314
315(* blackbox *)
316module DQSBUFM(
317	input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
318	input ECLK, SCLK,
319	input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4,
320	input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0,
321	input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
322	output DQSR90, DQSW, DQSW270,
323	output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
324	output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG
325);
326	parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
327	parameter DQS_LI_DEL_VAL = 0;
328	parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
329	parameter DQS_LO_DEL_VAL = 0;
330	parameter GSR = "ENABLED";
331endmodule
332
333(* blackbox *)
334module DDRDLLA(
335	input CLK, RST, UDDCNTLN, FREEZE,
336	output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
337);
338	parameter FORCE_MAX_DELAY = "NO";
339	parameter GSR = "ENABLED";
340endmodule
341
342(* blackbox *)
343module DLLDELD(
344	input A, DDRDEL, LOADN, MOVE, DIRECTION,
345	output Z, CFLAG
346);
347	parameter DEL_ADJ = "PLUS";
348	parameter DEL_VAL = 0;
349endmodule
350
351(* blackbox *)
352module CLKDIVF(
353	input CLKI, RST, ALIGNWD,
354	output CDIVX
355);
356	parameter GSR = "DISABLED";
357	parameter DIV = "2.0";
358endmodule
359
360(* blackbox *)
361module ECLKSYNCB(
362	input ECLKI, STOP,
363	output ECLKO
364);
365endmodule
366
367(* blackbox *)
368module ECLKBRIDGECS(
369	input CLK0, CLK1, SEL,
370	output ECSOUT
371);
372endmodule
373
374(* blackbox *)
375module DCCA(
376	input CLKI, CE,
377	output CLKO
378);
379endmodule
380
381(* blackbox *)
382module DCSC(
383	input CLK1, CLK0,
384	input SEL1, SEL0,
385	input MODESEL,
386	output DCSOUT
387);
388	parameter DCSMODE = "POS";
389endmodule
390
391(* blackbox *) (* keep *)
392module DCUA(
393	input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN,
394	input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,
395	input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,
396	input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,
397	input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,
398	input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,
399	input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,
400	input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,
401	input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,
402	input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,
403	input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,
404	input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,
405	input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,
406	input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,
407	input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,
408	input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,
409	input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,
410	input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,
411	input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,
412	input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,
413	output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,
414	output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,
415	output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,
416	output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,
417	output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,
418	output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,
419	output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,
420	output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,
421	output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,
422	output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,
423	output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,
424	output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,
425	output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,
426	output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,
427
428	input  D_REFCLKI,
429	output D_FFS_PLOL
430);
431	parameter CH0_AUTO_CALIB_EN = "0b0";
432	parameter CH0_AUTO_FACQ_EN = "0b0";
433	parameter CH0_BAND_THRESHOLD = "0b000000";
434	parameter CH0_CALIB_CK_MODE = "0b0";
435	parameter CH0_CC_MATCH_1 = "0b0000000000";
436	parameter CH0_CC_MATCH_2 = "0b0000000000";
437	parameter CH0_CC_MATCH_3 = "0b0000000000";
438	parameter CH0_CC_MATCH_4 = "0b0000000000";
439	parameter CH0_CDR_CNT4SEL = "0b00";
440	parameter CH0_CDR_CNT8SEL = "0b00";
441	parameter CH0_CTC_BYPASS = "0b0";
442	parameter CH0_DCOATDCFG = "0b00";
443	parameter CH0_DCOATDDLY = "0b00";
444	parameter CH0_DCOBYPSATD = "0b0";
445	parameter CH0_DCOCALDIV = "0b000";
446	parameter CH0_DCOCTLGI = "0b000";
447	parameter CH0_DCODISBDAVOID = "0b0";
448	parameter CH0_DCOFLTDAC = "0b00";
449	parameter CH0_DCOFTNRG = "0b000";
450	parameter CH0_DCOIOSTUNE = "0b000";
451	parameter CH0_DCOITUNE = "0b00";
452	parameter CH0_DCOITUNE4LSB = "0b000";
453	parameter CH0_DCOIUPDNX2 = "0b0";
454	parameter CH0_DCONUOFLSB = "0b000";
455	parameter CH0_DCOSCALEI = "0b00";
456	parameter CH0_DCOSTARTVAL = "0b000";
457	parameter CH0_DCOSTEP = "0b00";
458	parameter CH0_DEC_BYPASS = "0b0";
459	parameter CH0_ENABLE_CG_ALIGN = "0b0";
460	parameter CH0_ENC_BYPASS = "0b0";
461	parameter CH0_FF_RX_F_CLK_DIS = "0b0";
462	parameter CH0_FF_RX_H_CLK_EN = "0b0";
463	parameter CH0_FF_TX_F_CLK_DIS = "0b0";
464	parameter CH0_FF_TX_H_CLK_EN = "0b0";
465	parameter CH0_GE_AN_ENABLE = "0b0";
466	parameter CH0_INVERT_RX = "0b0";
467	parameter CH0_INVERT_TX = "0b0";
468	parameter CH0_LDR_CORE2TX_SEL = "0b0";
469	parameter CH0_LDR_RX2CORE_SEL = "0b0";
470	parameter CH0_LEQ_OFFSET_SEL = "0b0";
471	parameter CH0_LEQ_OFFSET_TRIM = "0b000";
472	parameter CH0_LSM_DISABLE = "0b0";
473	parameter CH0_MATCH_2_ENABLE = "0b0";
474	parameter CH0_MATCH_4_ENABLE = "0b0";
475	parameter CH0_MIN_IPG_CNT = "0b00";
476	parameter CH0_PCIE_EI_EN = "0b0";
477	parameter CH0_PCIE_MODE = "0b0";
478	parameter CH0_PCS_DET_TIME_SEL = "0b00";
479	parameter CH0_PDEN_SEL = "0b0";
480	parameter CH0_PRBS_ENABLE = "0b0";
481	parameter CH0_PRBS_LOCK = "0b0";
482	parameter CH0_PRBS_SELECTION = "0b0";
483	parameter CH0_RATE_MODE_RX = "0b0";
484	parameter CH0_RATE_MODE_TX = "0b0";
485	parameter CH0_RCV_DCC_EN = "0b0";
486	parameter CH0_REG_BAND_OFFSET = "0b0000";
487	parameter CH0_REG_BAND_SEL = "0b000000";
488	parameter CH0_REG_IDAC_EN = "0b0";
489	parameter CH0_REG_IDAC_SEL = "0b0000000000";
490	parameter CH0_REQ_EN = "0b0";
491	parameter CH0_REQ_LVL_SET = "0b00";
492	parameter CH0_RIO_MODE = "0b0";
493	parameter CH0_RLOS_SEL = "0b0";
494	parameter CH0_RPWDNB = "0b0";
495	parameter CH0_RTERM_RX = "0b00000";
496	parameter CH0_RTERM_TX = "0b00000";
497	parameter CH0_RXIN_CM = "0b00";
498	parameter CH0_RXTERM_CM = "0b00";
499	parameter CH0_RX_DCO_CK_DIV = "0b000";
500	parameter CH0_RX_DIV11_SEL = "0b0";
501	parameter CH0_RX_GEAR_BYPASS = "0b0";
502	parameter CH0_RX_GEAR_MODE = "0b0";
503	parameter CH0_RX_LOS_CEQ = "0b00";
504	parameter CH0_RX_LOS_EN = "0b0";
505	parameter CH0_RX_LOS_HYST_EN = "0b0";
506	parameter CH0_RX_LOS_LVL = "0b000";
507	parameter CH0_RX_RATE_SEL = "0b0000";
508	parameter CH0_RX_SB_BYPASS = "0b0";
509	parameter CH0_SB_BYPASS = "0b0";
510	parameter CH0_SEL_SD_RX_CLK = "0b0";
511	parameter CH0_TDRV_DAT_SEL = "0b00";
512	parameter CH0_TDRV_POST_EN = "0b0";
513	parameter CH0_TDRV_PRE_EN = "0b0";
514	parameter CH0_TDRV_SLICE0_CUR = "0b000";
515	parameter CH0_TDRV_SLICE0_SEL = "0b00";
516	parameter CH0_TDRV_SLICE1_CUR = "0b000";
517	parameter CH0_TDRV_SLICE1_SEL = "0b00";
518	parameter CH0_TDRV_SLICE2_CUR = "0b00";
519	parameter CH0_TDRV_SLICE2_SEL = "0b00";
520	parameter CH0_TDRV_SLICE3_CUR = "0b00";
521	parameter CH0_TDRV_SLICE3_SEL = "0b00";
522	parameter CH0_TDRV_SLICE4_CUR = "0b00";
523	parameter CH0_TDRV_SLICE4_SEL = "0b00";
524	parameter CH0_TDRV_SLICE5_CUR = "0b00";
525	parameter CH0_TDRV_SLICE5_SEL = "0b00";
526	parameter CH0_TPWDNB = "0b0";
527	parameter CH0_TX_CM_SEL = "0b00";
528	parameter CH0_TX_DIV11_SEL = "0b0";
529	parameter CH0_TX_GEAR_BYPASS = "0b0";
530	parameter CH0_TX_GEAR_MODE = "0b0";
531	parameter CH0_TX_POST_SIGN = "0b0";
532	parameter CH0_TX_PRE_SIGN = "0b0";
533	parameter CH0_UC_MODE = "0b0";
534	parameter CH0_UDF_COMMA_A = "0b0000000000";
535	parameter CH0_UDF_COMMA_B = "0b0000000000";
536	parameter CH0_UDF_COMMA_MASK = "0b0000000000";
537	parameter CH0_WA_BYPASS = "0b0";
538	parameter CH0_WA_MODE = "0b0";
539	parameter CH1_AUTO_CALIB_EN = "0b0";
540	parameter CH1_AUTO_FACQ_EN = "0b0";
541	parameter CH1_BAND_THRESHOLD = "0b000000";
542	parameter CH1_CALIB_CK_MODE = "0b0";
543	parameter CH1_CC_MATCH_1 = "0b0000000000";
544	parameter CH1_CC_MATCH_2 = "0b0000000000";
545	parameter CH1_CC_MATCH_3 = "0b0000000000";
546	parameter CH1_CC_MATCH_4 = "0b0000000000";
547	parameter CH1_CDR_CNT4SEL = "0b00";
548	parameter CH1_CDR_CNT8SEL = "0b00";
549	parameter CH1_CTC_BYPASS = "0b0";
550	parameter CH1_DCOATDCFG = "0b00";
551	parameter CH1_DCOATDDLY = "0b00";
552	parameter CH1_DCOBYPSATD = "0b0";
553	parameter CH1_DCOCALDIV = "0b000";
554	parameter CH1_DCOCTLGI = "0b000";
555	parameter CH1_DCODISBDAVOID = "0b0";
556	parameter CH1_DCOFLTDAC = "0b00";
557	parameter CH1_DCOFTNRG = "0b000";
558	parameter CH1_DCOIOSTUNE = "0b000";
559	parameter CH1_DCOITUNE = "0b00";
560	parameter CH1_DCOITUNE4LSB = "0b000";
561	parameter CH1_DCOIUPDNX2 = "0b0";
562	parameter CH1_DCONUOFLSB = "0b000";
563	parameter CH1_DCOSCALEI = "0b00";
564	parameter CH1_DCOSTARTVAL = "0b000";
565	parameter CH1_DCOSTEP = "0b00";
566	parameter CH1_DEC_BYPASS = "0b0";
567	parameter CH1_ENABLE_CG_ALIGN = "0b0";
568	parameter CH1_ENC_BYPASS = "0b0";
569	parameter CH1_FF_RX_F_CLK_DIS = "0b0";
570	parameter CH1_FF_RX_H_CLK_EN = "0b0";
571	parameter CH1_FF_TX_F_CLK_DIS = "0b0";
572	parameter CH1_FF_TX_H_CLK_EN = "0b0";
573	parameter CH1_GE_AN_ENABLE = "0b0";
574	parameter CH1_INVERT_RX = "0b0";
575	parameter CH1_INVERT_TX = "0b0";
576	parameter CH1_LDR_CORE2TX_SEL = "0b0";
577	parameter CH1_LDR_RX2CORE_SEL = "0b0";
578	parameter CH1_LEQ_OFFSET_SEL = "0b0";
579	parameter CH1_LEQ_OFFSET_TRIM = "0b000";
580	parameter CH1_LSM_DISABLE = "0b0";
581	parameter CH1_MATCH_2_ENABLE = "0b0";
582	parameter CH1_MATCH_4_ENABLE = "0b0";
583	parameter CH1_MIN_IPG_CNT = "0b00";
584	parameter CH1_PCIE_EI_EN = "0b0";
585	parameter CH1_PCIE_MODE = "0b0";
586	parameter CH1_PCS_DET_TIME_SEL = "0b00";
587	parameter CH1_PDEN_SEL = "0b0";
588	parameter CH1_PRBS_ENABLE = "0b0";
589	parameter CH1_PRBS_LOCK = "0b0";
590	parameter CH1_PRBS_SELECTION = "0b0";
591	parameter CH1_RATE_MODE_RX = "0b0";
592	parameter CH1_RATE_MODE_TX = "0b0";
593	parameter CH1_RCV_DCC_EN = "0b0";
594	parameter CH1_REG_BAND_OFFSET = "0b0000";
595	parameter CH1_REG_BAND_SEL = "0b000000";
596	parameter CH1_REG_IDAC_EN = "0b0";
597	parameter CH1_REG_IDAC_SEL = "0b0000000000";
598	parameter CH1_REQ_EN = "0b0";
599	parameter CH1_REQ_LVL_SET = "0b00";
600	parameter CH1_RIO_MODE = "0b0";
601	parameter CH1_RLOS_SEL = "0b0";
602	parameter CH1_RPWDNB = "0b0";
603	parameter CH1_RTERM_RX = "0b00000";
604	parameter CH1_RTERM_TX = "0b00000";
605	parameter CH1_RXIN_CM = "0b00";
606	parameter CH1_RXTERM_CM = "0b00";
607	parameter CH1_RX_DCO_CK_DIV = "0b000";
608	parameter CH1_RX_DIV11_SEL = "0b0";
609	parameter CH1_RX_GEAR_BYPASS = "0b0";
610	parameter CH1_RX_GEAR_MODE = "0b0";
611	parameter CH1_RX_LOS_CEQ = "0b00";
612	parameter CH1_RX_LOS_EN = "0b0";
613	parameter CH1_RX_LOS_HYST_EN = "0b0";
614	parameter CH1_RX_LOS_LVL = "0b000";
615	parameter CH1_RX_RATE_SEL = "0b0000";
616	parameter CH1_RX_SB_BYPASS = "0b0";
617	parameter CH1_SB_BYPASS = "0b0";
618	parameter CH1_SEL_SD_RX_CLK = "0b0";
619	parameter CH1_TDRV_DAT_SEL = "0b00";
620	parameter CH1_TDRV_POST_EN = "0b0";
621	parameter CH1_TDRV_PRE_EN = "0b0";
622	parameter CH1_TDRV_SLICE0_CUR = "0b000";
623	parameter CH1_TDRV_SLICE0_SEL = "0b00";
624	parameter CH1_TDRV_SLICE1_CUR = "0b000";
625	parameter CH1_TDRV_SLICE1_SEL = "0b00";
626	parameter CH1_TDRV_SLICE2_CUR = "0b00";
627	parameter CH1_TDRV_SLICE2_SEL = "0b00";
628	parameter CH1_TDRV_SLICE3_CUR = "0b00";
629	parameter CH1_TDRV_SLICE3_SEL = "0b00";
630	parameter CH1_TDRV_SLICE4_CUR = "0b00";
631	parameter CH1_TDRV_SLICE4_SEL = "0b00";
632	parameter CH1_TDRV_SLICE5_CUR = "0b00";
633	parameter CH1_TDRV_SLICE5_SEL = "0b00";
634	parameter CH1_TPWDNB = "0b0";
635	parameter CH1_TX_CM_SEL = "0b00";
636	parameter CH1_TX_DIV11_SEL = "0b0";
637	parameter CH1_TX_GEAR_BYPASS = "0b0";
638	parameter CH1_TX_GEAR_MODE = "0b0";
639	parameter CH1_TX_POST_SIGN = "0b0";
640	parameter CH1_TX_PRE_SIGN = "0b0";
641	parameter CH1_UC_MODE = "0b0";
642	parameter CH1_UDF_COMMA_A = "0b0000000000";
643	parameter CH1_UDF_COMMA_B = "0b0000000000";
644	parameter CH1_UDF_COMMA_MASK = "0b0000000000";
645	parameter CH1_WA_BYPASS = "0b0";
646	parameter CH1_WA_MODE = "0b0";
647	parameter D_BITCLK_FROM_ND_EN = "0b0";
648	parameter D_BITCLK_LOCAL_EN = "0b0";
649	parameter D_BITCLK_ND_EN = "0b0";
650	parameter D_BUS8BIT_SEL = "0b0";
651	parameter D_CDR_LOL_SET = "0b00";
652	parameter D_CMUSETBIASI = "0b00";
653	parameter D_CMUSETI4CPP = "0b0000";
654	parameter D_CMUSETI4CPZ = "0b0000";
655	parameter D_CMUSETI4VCO = "0b00";
656	parameter D_CMUSETICP4P = "0b00";
657	parameter D_CMUSETICP4Z = "0b000";
658	parameter D_CMUSETINITVCT = "0b00";
659	parameter D_CMUSETISCL4VCO = "0b000";
660	parameter D_CMUSETP1GM = "0b000";
661	parameter D_CMUSETP2AGM = "0b000";
662	parameter D_CMUSETZGM = "0b000";
663	parameter D_DCO_CALIB_TIME_SEL = "0b00";
664	parameter D_HIGH_MARK = "0b0000";
665	parameter D_IB_PWDNB = "0b0";
666	parameter D_ISETLOS = "0b00000000";
667	parameter D_LOW_MARK = "0b0000";
668	parameter D_MACROPDB = "0b0";
669	parameter D_PD_ISET = "0b00";
670	parameter D_PLL_LOL_SET = "0b00";
671	parameter D_REFCK_MODE = "0b000";
672	parameter D_REQ_ISET = "0b000";
673	parameter D_RG_EN = "0b0";
674	parameter D_RG_SET = "0b00";
675	parameter D_SETICONST_AUX = "0b00";
676	parameter D_SETICONST_CH = "0b00";
677	parameter D_SETIRPOLY_AUX = "0b00";
678	parameter D_SETIRPOLY_CH = "0b00";
679	parameter D_SETPLLRC = "0b000000";
680	parameter D_SYNC_LOCAL_EN = "0b0";
681	parameter D_SYNC_ND_EN = "0b0";
682	parameter D_TXPLL_PWDNB = "0b0";
683	parameter D_TX_VCO_CK_DIV = "0b000";
684	parameter D_XGE_MODE = "0b0";
685
686// These parameters don't do anything but are
687// needed for compatibility with Diamond
688	parameter D_TX_MAX_RATE = "2.5";
689	parameter D_RX_MAX_RATE = "2.5";
690	parameter CH0_TXAMPLITUDE = "0d1300";
691	parameter CH1_TXAMPLITUDE = "0d1300";
692	parameter CH0_PROTOCOL = "8B10B";
693	parameter CH1_PROTOCOL = "8B10B";
694	parameter CH0_CDR_MAX_RATE = "2.5";
695	parameter CH1_CDR_MAX_RATE = "2.5";
696	parameter CH0_TXDEPRE = "DISABLED";
697	parameter CH1_TXDEPRE = "DISABLED";
698	parameter CH0_TXDEPOST = "DISABLED";
699	parameter CH1_TXDEPOST = "DISABLED";
700endmodule
701
702(* blackbox *)
703module EXTREFB (
704	input  REFCLKP, REFCLKN,
705	output REFCLKO
706);
707	parameter REFCK_PWDNB = "0b0";
708	parameter REFCK_RTERM = "0b0";
709	parameter REFCK_DCBIAS_EN = "0b0";
710endmodule
711
712(* blackbox *)
713module PCSCLKDIV (
714	input CLKI, RST, SEL2, SEL1, SEL0,
715	output CDIV1, CDIVX
716);
717	parameter GSR = "DISABLED";
718endmodule
719
720// Note: this module is not marked keep as we want it swept away in synth (sim use only)
721(* blackbox *)
722module PUR (
723	input PUR
724);
725	parameter RST_PULSE = 1;
726endmodule
727
728(* blackbox, keep *)
729module GSR (
730	input GSR
731);
732endmodule
733
734(* blackbox, keep *)
735module SGSR (
736	input GSR, CLK
737);
738endmodule
739
740
741(* blackbox *)
742module PDPW16KD (
743	input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18,
744	input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
745	input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
746	input BE3,  BE2,  BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0,
747	input ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0,
748	input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
749	output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18,
750	output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
751);
752	parameter DATA_WIDTH_W = 36;
753	parameter DATA_WIDTH_R = 36;
754	parameter GSR = "ENABLED";
755
756	parameter REGMODE = "NOREG";
757
758	parameter RESETMODE = "SYNC";
759	parameter ASYNC_RESET_RELEASE = "SYNC";
760
761	parameter CSDECODE_W = "0b000";
762	parameter CSDECODE_R = "0b000";
763
764	parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
765	parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
766	parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
767	parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
768	parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
769	parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
770	parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
771	parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
772	parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
773	parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
774	parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
775	parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
776	parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
777	parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
778	parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
779	parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
780	parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
781	parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
782	parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
783	parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
784	parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
785	parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
786	parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
787	parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
788	parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
789	parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
790	parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
791	parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
792	parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
793	parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
794	parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
795	parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
796	parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
797	parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
798	parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
799	parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
800	parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
801	parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
802	parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
803	parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
804	parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
805	parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
806	parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
807	parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
808	parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
809	parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
810	parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
811	parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
812	parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
813	parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
814	parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
815	parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
816	parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
817	parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
818	parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
819	parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
820	parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
821	parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
822	parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
823	parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
824	parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
825	parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
826	parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
827	parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
828	parameter INIT_DATA = "STATIC";
829	parameter CLKWMUX = "CLKW";
830	parameter CLKRMUX = "CLKR";
831
832endmodule
833