1read_verilog test_arith.v 2synth_ice40 3rename test gate 4 5read_verilog test_arith.v 6rename test gold 7 8miter -equiv -flatten -make_outputs gold gate miter 9sat -verify -prove trigger 0 -show-ports miter 10 11synth_ice40 -top gate 12 13read_verilog test_arith.v 14rename test gold 15 16miter -equiv -flatten -make_outputs gold gate miter 17sat -verify -prove trigger 0 -show-ports miter 18