1read_verilog ../common/dffs.v 2rename dff my_dff # Work around conflicting module names between test and vendor cells 3rename dffe my_dffe 4design -save read 5 6hierarchy -top my_dff 7proc 8equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check 9design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 10cd dff # Constrain all select calls below inside the top module 11select -assert-none t:* 12 13design -load read 14hierarchy -top my_dffe 15proc 16equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check 17design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 18cd dffe # Constrain all select calls below inside the top module 19 20select -assert-none t:*