1module opt_share_test(
2  input [15:0]      a,
3  input [15:0]      b,
4  input [15:0]      c,
5  input [15:0]      d,
6  input             sel,
7  output reg [47:0] res,
8  );
9
10  wire [15:0]       add_res = a+b;
11  wire [15:0]       sub_res = a-b;
12  wire [31: 0]      cat1 = {add_res, c+d};
13  wire [31: 0]      cat2 = {sub_res, c-d};
14
15  always @* begin
16    case(sel)
17      0: res = {cat1, add_res};
18      1: res = {cat2, add_res};
19    endcase
20  end
21
22endmodule
23