1function [7:0] do_add;
2  input [7:0] inp_a;
3  input [7:0] inp_b;
4
5  do_add = inp_a + inp_b;
6
7endfunction
8
9module foo(clk, rst, inp_a, inp_b, out);
10  input  wire clk;
11  input  wire rst;
12  input  wire [7:0] inp_a;
13  input  wire [7:0] inp_b;
14  output reg  [7:0] out;
15
16  always @(posedge clk)
17    if (rst) out <= 0;
18    else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
19
20endmodule
21
22