1read_verilog <<EOT
2
3module top(input clk, input rst);
4
5reg [1:0] state;
6
7always @(posedge clk, posedge rst) begin
8	if (rst)
9		state <= 0;
10	else
11		case (state)
12			2'b00: state <= 2'b01;
13			2'b01: state <= 2'b10;
14			2'b10: state <= 2'b00;
15		endcase
16end
17
18sub sub_i(.i(state == 0));
19
20endmodule
21
22
23(* blackbox, keep *)
24module sub(input i);
25endmodule
26
27EOT
28
29proc
30fsm
31
32# Make sure there is a driver
33select -assert-any t:sub %ci %a w:* %i %ci c:* %i
34