1read_verilog -nomem2reg port_sign_extend.v 2hierarchy 3flatten 4proc 5memory 6equiv_make ref act equiv 7equiv_simple 8equiv_status -assert 9 10delete 11 12read_verilog -nomem2reg port_sign_extend.v 13flatten 14proc 15memory 16equiv_make ref act equiv 17equiv_simple 18equiv_status -assert 19 20delete 21 22read_verilog -nomem2reg port_sign_extend.v 23hierarchy 24proc 25memory 26equiv_make ref act equiv 27prep -flatten -top equiv 28equiv_induct 29equiv_status -assert 30