1read_verilog shregmap.v 2design -save read 3 4design -copy-to model $__SHREG_DFF_P_ 5hierarchy -top shregmap_static_test 6prep 7design -save gold 8 9techmap 10shregmap -init 11 12opt 13 14# stat 15# show -width 16select -assert-count 1 t:$_DFF_P_ 17select -assert-count 2 t:$__SHREG_DFF_P_ 18 19design -stash gate 20 21design -import gold -as gold 22design -import gate -as gate 23design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_ 24prep 25 26miter -equiv -flatten -make_assert -make_outputs gold gate miter 27sat -verify -prove-asserts -show-ports -seq 5 miter 28 29#design -load gold 30#stat 31 32#design -load gate 33#stat 34