1read_verilog -specify <<EOT 2module buffer(input i, output o); 3specify 4(i => o) = 10; 5endspecify 6endmodule 7 8module top(input i); 9wire w; 10buffer b(.i(i), .o(w)); 11endmodule 12EOT 13 14logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1 15sta 16 17 18design -reset 19read_verilog -specify <<EOT 20module top(input i, output o, p); 21assign o = i; 22endmodule 23EOT 24 25logger -expect log "No timing paths found\." 1 26sta 27 28 29design -reset 30read_verilog -specify <<EOT 31module buffer(input i, output o); 32specify 33(i => o) = 10; 34endspecify 35endmodule 36 37module top(input i, output o, p); 38buffer b(.i(i), .o(o)); 39endmodule 40EOT 41 42sta 43 44 45design -reset 46read_verilog -specify <<EOT 47module buffer(input i, output o); 48specify 49(i => o) = 10; 50endspecify 51endmodule 52 53module top(input i, output o, p); 54buffer b(.i(i), .o(o)); 55const0 c(.o(p)); 56endmodule 57EOT 58 59logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1 60sta 61 62 63design -reset 64read_verilog -specify <<EOT 65module buffer(input i, output o); 66specify 67(i => o) = 10; 68endspecify 69endmodule 70module const0(output o); 71endmodule 72 73module top(input i, output o, p); 74buffer b(.i(i), .o(o)); 75const0 c(.o(p)); 76endmodule 77EOT 78 79sta 80 81logger -expect-no-warnings 82