1logger -expect-no-warnings 2read_verilog <<EOT 3module test (a, b, c, y); 4 input a; 5 input signed [1:0] b; 6 input signed [2:0] c; 7 output y; 8 assign #(12.5 : 14.5 : 20) y = ^(a ? b : c); 9endmodule 10EOT 11 12design -reset 13logger -expect-no-warnings 14read_verilog << EOT 15module test (input [7:0] a, b, c, d, output [7:0] x, y, z); 16 assign #(20:20:25) x = a + b, y = b + c, z = c + d; 17endmodule 18EOT 19 20design -reset 21logger -expect-no-warnings 22read_verilog << EOT 23module test (input [7:0] a, b, c, d, output [7:0] x, y, z); 24 assign #(20:20:25, 40:45:50, 60:65:75) x = a + b, y = b + c, z = c + d; 25endmodule 26EOT 27 28design -reset 29logger -expect-no-warnings 30read_verilog <<EOT 31module test (a, b, c, y); 32 localparam TIME_STEP = 0.011; 33 input signed [3:0] a; 34 input signed [1:0] b; 35 input signed [1:0] c; 36 output [5:0] y; 37 assign #(TIME_STEP:TIME_STEP:TIME_STEP) y = (a >> b) >>> c; 38endmodule 39EOT 40 41design -reset 42logger -expect-no-warnings 43read_verilog <<EOT 44module test; 45 wire o, a, b; 46 and #(1:2:3, 4:5:6) and_gate (o, a, b); 47 wire #(1:2:3, 4:5:6, 7:8:9) x; 48 assign o = x; 49endmodule 50EOT 51 52design -reset 53logger -expect-no-warnings 54read_verilog <<EOT 55module test; 56 localparam TIME_TYP = 0.7; 57 wire o, a, b; 58 and #(0:TIME_TYP:2) and_gate (o, a, b); 59 wire #(2:TIME_TYP:4) x; 60 assign o = x; 61endmodule 62EOT 63 64design -reset 65logger -expect warning "Yosys has only limited support for tri-state logic at the moment." 1 66read_verilog <<EOT 67module test (input en, input a, input b, output c); 68 wire [15:0] add0_res = a + b; 69 assign #(15:20:30) c = (en) ? a : 1'bz; 70endmodule 71EOT 72 73design -reset 74logger -expect-no-warnings 75read_verilog <<EOT 76module test (input en, d, t_min, t, t_max); 77 reg o; 78 always @* 79 if (en) 80 o = #(t_min : t : t_max, t_min : t : t_max) ~d; 81endmodule 82EOT 83 84design -reset 85logger -expect-no-warnings 86read_verilog <<EOT 87module test #(parameter DELAY_RISE = 0, DELAY_FALL = 0, DELAY_Z = 0) 88 (input clock, input reset, input req_0, input req_1, output gnt_0, output gnt_1); 89 parameter SIZE = 3; 90 parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100; 91 reg [SIZE-1:0] state; 92 reg [SIZE-1:0] next_state; 93 reg gnt_0, gnt_1; 94 95 always @ (state or req_0 or req_1) 96 begin : FSM_COMBO 97 next_state = 3'b000; 98 case (state) 99 IDLE : if (req_0 == 1'b1) begin 100 next_state = #(DELAY_RISE-1 : DELAY_RISE : DELAY_RISE+1) GNT0; 101 end else if (req_1 == 1'b1) begin 102 next_state = #(DELAY_FALL/1.2 : DELAY_FALL : DELAY_FALL*2.5) GNT1; 103 end else begin 104 next_state = #(DELAY_Z : DELAY_Z : DELAY_Z) IDLE; 105 end 106 GNT0 : if (req_0 == 1'b1) begin 107 #(DELAY_RISE : DELAY_RISE : DELAY_FALL) next_state = GNT0; 108 end else begin 109 #DELAY_RISE next_state = IDLE; 110 end 111 GNT1 : if (req_1 == 1'b1) begin 112 #10 next_state = GNT1; 113 end else begin 114 #(10:10:15, 20:25:25) next_state = IDLE; 115 end 116 default : next_state = IDLE; 117 endcase 118 end 119 120 always @ (posedge clock) 121 begin : FSM_SEQ 122 if (reset == 1'b1) begin 123 #(10:10:15) state <= IDLE; 124 end else begin 125 #(10) state <= next_state; 126 end 127 end 128 129 always @ (posedge clock) 130 begin : FSM_OUTPUT 131 if (reset == 1'b1) begin 132 gnt_0 <= #(8:9:10) 1'b0; 133 gnt_1 <= #1 1'b0; 134 end else begin 135 case (state) 136 IDLE : begin 137 gnt_0 <= #(8:9:10) 1'b0; 138 gnt_1 <= #1 1'b0; 139 end 140 GNT0 : begin 141 gnt_0 <= #(4:5:6,8:9:10) 1'b1; 142 gnt_1 <= #1 1'b0; 143 end 144 GNT1 : begin 145 gnt_0 <= #(2:3:4,4:5:6,8:9:10) 1'b0; 146 gnt_1 <= #1 1'b1; 147 end 148 default : begin 149 gnt_0 <= 1'b0; 150 gnt_1 <= 1'b0; 151 end 152 endcase 153 end 154 end 155endmodule 156EOT 157 158design -reset 159logger -expect-no-warnings 160read_verilog <<EOT 161module test; 162 reg q; 163 initial begin 164 q = 1; 165 #(1:2:2) q = 0; 166 end 167endmodule 168EOT 169 170design -reset 171logger -expect-no-warnings 172read_verilog <<EOT 173module test #(parameter hyst = 16) 174 (input [0:1] inA, input rst, output reg out); 175 parameter real updatePeriod = 100.0; 176 initial out = 1'b0; 177 always #(updatePeriod-5:updatePeriod:updatePeriod+5) begin 178 if (rst) out <= 1'b0; 179 else if (inA[0] > inA[1]) out <= 1'b1; 180 else if (inA[0] < inA[1] - hyst) out <= 1'b0; 181 end 182endmodule 183EOT 184 185design -reset 186logger -expect-no-warnings 187read_verilog <<EOT 188module test; 189 reg clk; 190 initial clk = 1'b0; 191 always #(100:180:230) clk = ~clk; 192endmodule 193EOT 194 195design -reset 196logger -expect-no-warnings 197read_verilog <<EOT 198module test; 199 reg clk; 200 initial clk = 1'b0; 201 always clk = #(100:180:230, 100:180:230) ~clk; 202 task t_test; 203 sig_036_A <= #(2, 4, 5.5) 0; 204 sig_036_B <= #(1.3, 3) 0; 205 sig_036_S <= #(2) 0; 206 #(100 : 200 : 300, 400 : 500 : 600, 700 : 800 : 900); 207 sig_036_A <= #(1.5:2.5:3.0, 3:4:5, 7) ~0; 208 sig_036_B <= #(2, 4:6:6) ~0; 209 sig_036_S <= #(1.5:2.5:3.0) ~0; 210 #100; 211 endtask 212endmodule 213EOT 214