1// -*- verilog -*-
2//
3//  USRP - Universal Software Radio Peripheral
4//
5//  Copyright (C) 2003 Matt Ettus
6//
7//  This program is free software; you can redistribute it and/or modify
8//  it under the terms of the GNU General Public License as published by
9//  the Free Software Foundation; either version 2 of the License, or
10//  (at your option) any later version.
11//
12//  This program is distributed in the hope that it will be useful,
13//  but WITHOUT ANY WARRANTY; without even the implied warranty of
14//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15//  GNU General Public License for more details.
16//
17//  You should have received a copy of the GNU General Public License
18//  along with this program; if not, write to the Free Software
19//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20//
21
22
23
24module strobe_gen
25  ( input clock,
26    input reset,
27    input enable,
28    input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
29    input strobe_in,
30    output wire strobe );
31
32//   parameter width = 8;
33
34   reg [7:0] counter;
35   assign strobe = ~|counter && enable && strobe_in;
36
37   always @(posedge clock)
38     if(reset | ~enable)
39       counter <= #1 8'd0;
40     else if(strobe_in)
41       if(counter == 0)
42	 counter <= #1 rate;
43       else
44	 counter <= #1 counter - 8'd1;
45
46endmodule // strobe_gen
47