1# Copyright (C) 1991-2005 Altera Corporation 2# Your use of Altera Corporation's design tools, logic functions 3# and other software and tools, and its AMPP partner logic 4# functions, and any output files any of the foregoing 5# (including device programming or simulation files), and any 6# associated documentation or information are expressly subject 7# to the terms and conditions of the Altera Program License 8# Subscription Agreement, Altera MegaCore Function License 9# Agreement, or other applicable license agreement, including, 10# without limitation, that your use is for the sole purpose of 11# programming logic devices manufactured by Altera and sold by 12# Altera or its authorized distributors. Please refer to the 13# applicable agreement for further details. 14 15 16# The default values for assignments are stored in the file 17# mrfm_assignment_defaults.qdf 18# If this file doesn't exist, and for assignments not listed, see file 19# assignment_defaults.qdf 20 21# Altera recommends that you do not modify this file. This 22# file is updated automatically by the Quartus II software 23# and any changes you make may be lost or overwritten. 24 25 26# Project-Wide Assignments 27# ======================== 28set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 29set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" 30set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2" 31 32# Pin & Location Assignments 33# ========================== 34set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" 35set_location_assignment PIN_29 -to SCLK 36set_location_assignment PIN_117 -to SDI 37set_location_assignment PIN_28 -to usbclk 38set_location_assignment PIN_107 -to usbctl[0] 39set_location_assignment PIN_106 -to usbctl[1] 40set_location_assignment PIN_105 -to usbctl[2] 41set_location_assignment PIN_100 -to usbdata[0] 42set_location_assignment PIN_84 -to usbdata[10] 43set_location_assignment PIN_83 -to usbdata[11] 44set_location_assignment PIN_82 -to usbdata[12] 45set_location_assignment PIN_79 -to usbdata[13] 46set_location_assignment PIN_78 -to usbdata[14] 47set_location_assignment PIN_77 -to usbdata[15] 48set_location_assignment PIN_99 -to usbdata[1] 49set_location_assignment PIN_98 -to usbdata[2] 50set_location_assignment PIN_95 -to usbdata[3] 51set_location_assignment PIN_94 -to usbdata[4] 52set_location_assignment PIN_93 -to usbdata[5] 53set_location_assignment PIN_88 -to usbdata[6] 54set_location_assignment PIN_87 -to usbdata[7] 55set_location_assignment PIN_86 -to usbdata[8] 56set_location_assignment PIN_85 -to usbdata[9] 57set_location_assignment PIN_104 -to usbrdy[0] 58set_location_assignment PIN_101 -to usbrdy[1] 59set_location_assignment PIN_76 -to FX2_1 60set_location_assignment PIN_75 -to FX2_2 61set_location_assignment PIN_74 -to FX2_3 62set_location_assignment PIN_116 -to io_rx_a[0] 63set_location_assignment PIN_115 -to io_rx_a[1] 64set_location_assignment PIN_114 -to io_rx_a[2] 65set_location_assignment PIN_113 -to io_rx_a[3] 66set_location_assignment PIN_108 -to io_rx_a[4] 67set_location_assignment PIN_195 -to io_rx_a[5] 68set_location_assignment PIN_196 -to io_rx_a[6] 69set_location_assignment PIN_197 -to io_rx_a[7] 70set_location_assignment PIN_200 -to io_rx_a[8] 71set_location_assignment PIN_201 -to io_rx_a[9] 72set_location_assignment PIN_202 -to io_rx_a[10] 73set_location_assignment PIN_203 -to io_rx_a[11] 74set_location_assignment PIN_206 -to io_rx_a[12] 75set_location_assignment PIN_207 -to io_rx_a[13] 76set_location_assignment PIN_208 -to io_rx_a[14] 77set_location_assignment PIN_214 -to io_rx_b[0] 78set_location_assignment PIN_215 -to io_rx_b[1] 79set_location_assignment PIN_216 -to io_rx_b[2] 80set_location_assignment PIN_217 -to io_rx_b[3] 81set_location_assignment PIN_218 -to io_rx_b[4] 82set_location_assignment PIN_219 -to io_rx_b[5] 83set_location_assignment PIN_222 -to io_rx_b[6] 84set_location_assignment PIN_223 -to io_rx_b[7] 85set_location_assignment PIN_224 -to io_rx_b[8] 86set_location_assignment PIN_225 -to io_rx_b[9] 87set_location_assignment PIN_226 -to io_rx_b[10] 88set_location_assignment PIN_227 -to io_rx_b[11] 89set_location_assignment PIN_228 -to io_rx_b[12] 90set_location_assignment PIN_233 -to io_rx_b[13] 91set_location_assignment PIN_234 -to io_rx_b[14] 92set_location_assignment PIN_175 -to io_tx_a[0] 93set_location_assignment PIN_176 -to io_tx_a[1] 94set_location_assignment PIN_177 -to io_tx_a[2] 95set_location_assignment PIN_178 -to io_tx_a[3] 96set_location_assignment PIN_179 -to io_tx_a[4] 97set_location_assignment PIN_180 -to io_tx_a[5] 98set_location_assignment PIN_181 -to io_tx_a[6] 99set_location_assignment PIN_182 -to io_tx_a[7] 100set_location_assignment PIN_183 -to io_tx_a[8] 101set_location_assignment PIN_184 -to io_tx_a[9] 102set_location_assignment PIN_185 -to io_tx_a[10] 103set_location_assignment PIN_186 -to io_tx_a[11] 104set_location_assignment PIN_187 -to io_tx_a[12] 105set_location_assignment PIN_188 -to io_tx_a[13] 106set_location_assignment PIN_193 -to io_tx_a[14] 107set_location_assignment PIN_73 -to io_tx_b[0] 108set_location_assignment PIN_68 -to io_tx_b[1] 109set_location_assignment PIN_67 -to io_tx_b[2] 110set_location_assignment PIN_66 -to io_tx_b[3] 111set_location_assignment PIN_65 -to io_tx_b[4] 112set_location_assignment PIN_64 -to io_tx_b[5] 113set_location_assignment PIN_63 -to io_tx_b[6] 114set_location_assignment PIN_62 -to io_tx_b[7] 115set_location_assignment PIN_61 -to io_tx_b[8] 116set_location_assignment PIN_60 -to io_tx_b[9] 117set_location_assignment PIN_59 -to io_tx_b[10] 118set_location_assignment PIN_58 -to io_tx_b[11] 119set_location_assignment PIN_57 -to io_tx_b[12] 120set_location_assignment PIN_56 -to io_tx_b[13] 121set_location_assignment PIN_55 -to io_tx_b[14] 122set_location_assignment PIN_152 -to master_clk 123set_location_assignment PIN_144 -to rx_a_a[0] 124set_location_assignment PIN_143 -to rx_a_a[1] 125set_location_assignment PIN_141 -to rx_a_a[2] 126set_location_assignment PIN_140 -to rx_a_a[3] 127set_location_assignment PIN_139 -to rx_a_a[4] 128set_location_assignment PIN_138 -to rx_a_a[5] 129set_location_assignment PIN_137 -to rx_a_a[6] 130set_location_assignment PIN_136 -to rx_a_a[7] 131set_location_assignment PIN_135 -to rx_a_a[8] 132set_location_assignment PIN_134 -to rx_a_a[9] 133set_location_assignment PIN_133 -to rx_a_a[10] 134set_location_assignment PIN_132 -to rx_a_a[11] 135set_location_assignment PIN_23 -to rx_a_b[0] 136set_location_assignment PIN_21 -to rx_a_b[1] 137set_location_assignment PIN_20 -to rx_a_b[2] 138set_location_assignment PIN_19 -to rx_a_b[3] 139set_location_assignment PIN_18 -to rx_a_b[4] 140set_location_assignment PIN_17 -to rx_a_b[5] 141set_location_assignment PIN_16 -to rx_a_b[6] 142set_location_assignment PIN_15 -to rx_a_b[7] 143set_location_assignment PIN_14 -to rx_a_b[8] 144set_location_assignment PIN_13 -to rx_a_b[9] 145set_location_assignment PIN_12 -to rx_a_b[10] 146set_location_assignment PIN_11 -to rx_a_b[11] 147set_location_assignment PIN_131 -to rx_b_a[0] 148set_location_assignment PIN_128 -to rx_b_a[1] 149set_location_assignment PIN_127 -to rx_b_a[2] 150set_location_assignment PIN_126 -to rx_b_a[3] 151set_location_assignment PIN_125 -to rx_b_a[4] 152set_location_assignment PIN_124 -to rx_b_a[5] 153set_location_assignment PIN_123 -to rx_b_a[6] 154set_location_assignment PIN_122 -to rx_b_a[7] 155set_location_assignment PIN_121 -to rx_b_a[8] 156set_location_assignment PIN_120 -to rx_b_a[9] 157set_location_assignment PIN_119 -to rx_b_a[10] 158set_location_assignment PIN_118 -to rx_b_a[11] 159set_location_assignment PIN_8 -to rx_b_b[0] 160set_location_assignment PIN_7 -to rx_b_b[1] 161set_location_assignment PIN_6 -to rx_b_b[2] 162set_location_assignment PIN_5 -to rx_b_b[3] 163set_location_assignment PIN_4 -to rx_b_b[4] 164set_location_assignment PIN_3 -to rx_b_b[5] 165set_location_assignment PIN_2 -to rx_b_b[6] 166set_location_assignment PIN_240 -to rx_b_b[7] 167set_location_assignment PIN_239 -to rx_b_b[8] 168set_location_assignment PIN_238 -to rx_b_b[9] 169set_location_assignment PIN_237 -to rx_b_b[10] 170set_location_assignment PIN_236 -to rx_b_b[11] 171set_location_assignment PIN_156 -to SDO 172set_location_assignment PIN_153 -to SEN_FPGA 173set_location_assignment PIN_159 -to tx_a[0] 174set_location_assignment PIN_160 -to tx_a[1] 175set_location_assignment PIN_161 -to tx_a[2] 176set_location_assignment PIN_162 -to tx_a[3] 177set_location_assignment PIN_163 -to tx_a[4] 178set_location_assignment PIN_164 -to tx_a[5] 179set_location_assignment PIN_165 -to tx_a[6] 180set_location_assignment PIN_166 -to tx_a[7] 181set_location_assignment PIN_167 -to tx_a[8] 182set_location_assignment PIN_168 -to tx_a[9] 183set_location_assignment PIN_169 -to tx_a[10] 184set_location_assignment PIN_170 -to tx_a[11] 185set_location_assignment PIN_173 -to tx_a[12] 186set_location_assignment PIN_174 -to tx_a[13] 187set_location_assignment PIN_38 -to tx_b[0] 188set_location_assignment PIN_39 -to tx_b[1] 189set_location_assignment PIN_41 -to tx_b[2] 190set_location_assignment PIN_42 -to tx_b[3] 191set_location_assignment PIN_43 -to tx_b[4] 192set_location_assignment PIN_44 -to tx_b[5] 193set_location_assignment PIN_45 -to tx_b[6] 194set_location_assignment PIN_46 -to tx_b[7] 195set_location_assignment PIN_47 -to tx_b[8] 196set_location_assignment PIN_48 -to tx_b[9] 197set_location_assignment PIN_49 -to tx_b[10] 198set_location_assignment PIN_50 -to tx_b[11] 199set_location_assignment PIN_53 -to tx_b[12] 200set_location_assignment PIN_54 -to tx_b[13] 201set_location_assignment PIN_158 -to TXSYNC_A 202set_location_assignment PIN_37 -to TXSYNC_B 203set_location_assignment PIN_235 -to io_rx_b[15] 204set_location_assignment PIN_24 -to io_tx_b[15] 205set_location_assignment PIN_213 -to io_rx_a[15] 206set_location_assignment PIN_194 -to io_tx_a[15] 207set_location_assignment PIN_1 -to MYSTERY_SIGNAL 208 209# Timing Assignments 210# ================== 211set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF 212 213# Analysis & Synthesis Assignments 214# ================================ 215set_global_assignment -name SAVE_DISK_SPACE OFF 216set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" 217set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 218set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>" 219set_global_assignment -name FAMILY Cyclone 220set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED 221set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED 222set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED 223set_global_assignment -name TOP_LEVEL_ENTITY mrfm 224set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF 225set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" 226set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON 227 228# Fitter Assignments 229# ================== 230set_global_assignment -name DEVICE EP1C12Q240C8 231set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" 232set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" 233set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF 234set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" 235set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON 236set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON 237set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON 238set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF 239set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA 240set_global_assignment -name INC_PLC_MODE OFF 241set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF 242set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] 243set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL 244set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 245 246# Timing Analysis Assignments 247# =========================== 248set_global_assignment -name MAX_SCC_SIZE 50 249 250# EDA Netlist Writer Assignments 251# ============================== 252set_global_assignment -name EDA_SIMULATION_TOOL "<None>" 253set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>" 254set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>" 255set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>" 256set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>" 257 258# Assembler Assignments 259# ===================== 260set_global_assignment -name USE_CONFIGURATION_DEVICE OFF 261set_global_assignment -name GENERATE_RBF_FILE ON 262set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" 263set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF 264 265# Simulator Assignments 266# ===================== 267set_global_assignment -name START_TIME "0 ns" 268set_global_assignment -name GLITCH_INTERVAL "1 ns" 269 270# Design Assistant Assignments 271# ============================ 272set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF 273set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF 274set_global_assignment -name ASSG_CAT OFF 275set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF 276set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF 277set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF 278set_global_assignment -name CLK_CAT OFF 279set_global_assignment -name CLK_RULE_COMB_CLOCK OFF 280set_global_assignment -name CLK_RULE_INV_CLOCK OFF 281set_global_assignment -name CLK_RULE_GATING_SCHEME OFF 282set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF 283set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF 284set_global_assignment -name CLK_RULE_MIX_EDGES OFF 285set_global_assignment -name RESET_CAT OFF 286set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF 287set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF 288set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF 289set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF 290set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF 291set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF 292set_global_assignment -name TIMING_CAT OFF 293set_global_assignment -name TIMING_RULE_SHIFT_REG OFF 294set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF 295set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF 296set_global_assignment -name NONSYNCHSTRUCT_CAT OFF 297set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF 298set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF 299set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF 300set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF 301set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF 302set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF 303set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF 304set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF 305set_global_assignment -name SIGNALRACE_CAT OFF 306set_global_assignment -name ACLK_CAT OFF 307set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF 308set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF 309set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF 310set_global_assignment -name HCPY_CAT OFF 311set_global_assignment -name HCPY_VREF_PINS OFF 312 313# SignalTap II Assignments 314# ======================== 315set_global_assignment -name HUB_ENTITY_NAME SLD_HUB 316set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST 317set_global_assignment -name ENABLE_SIGNALTAP OFF 318 319# LogicLock Region Assignments 320# ============================ 321set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF 322 323# ----------------- 324# start CLOCK(SCLK) 325 326 # Timing Assignments 327 # ================== 328set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK 329set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK 330set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK 331 332# end CLOCK(SCLK) 333# --------------- 334 335# ----------------------- 336# start CLOCK(master_clk) 337 338 # Timing Assignments 339 # ================== 340set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk 341set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk 342set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk 343 344# end CLOCK(master_clk) 345# --------------------- 346 347# ------------------- 348# start CLOCK(usbclk) 349 350 # Timing Assignments 351 # ================== 352set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk 353set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk 354set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk 355 356# end CLOCK(usbclk) 357# ----------------- 358 359# ---------------------- 360# start ENTITY(mrfm) 361 362 # Timing Assignments 363 # ================== 364set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK 365set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk 366set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk 367 368# end ENTITY(mrfm) 369# -------------------- 370 371 372set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON 373set_global_assignment -name SMART_RECOMPILE ON 374set_global_assignment -name VERILOG_FILE mrfm.vh 375set_global_assignment -name VERILOG_FILE biquad_2stage.v 376set_global_assignment -name VERILOG_FILE mrfm_compensator.v 377set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v 378set_global_assignment -name VERILOG_FILE mrfm_proc.v 379set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v 380set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v 381set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v 382set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v 383set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v 384set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v 385set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v 386set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v 387set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v 388set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v 389set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v 390set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v 391set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v 392set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v 393set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v 394set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v 395set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v 396set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v 397set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v 398set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v 399set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v 400set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v 401set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v 402set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v 403set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v 404set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v 405set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v 406set_global_assignment -name VERILOG_FILE mrfm.v 407set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v 408set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v 409set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v 410set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v 411set_global_assignment -name FITTER_EFFORT "STANDARD FIT"