1# 2# Copyright 2010-2012 Ettus Research LLC 3# 4 5################################################## 6# Control Lib Sources 7################################################## 8CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../control_lib/, \ 9CRC16_D16.v \ 10atr_controller.v \ 11bin2gray.v \ 12dcache.v \ 13decoder_3_8.v \ 14dbsm.v \ 15dpram32.v \ 16double_buffer.v \ 17gray2bin.v \ 18gray_send.v \ 19icache.v \ 20mux4.v \ 21mux8.v \ 22nsgpio.v \ 23ram_2port.v \ 24ram_harv_cache.v \ 25ram_harvard.v \ 26ram_harvard2.v \ 27ram_loader.v \ 28setting_reg.v \ 29settings_bus.v \ 30settings_bus_crossclock.v \ 31srl.v \ 32system_control.v \ 33wb_1master.v \ 34wb_readback_mux.v \ 35wb_readback_mux_16LE.v \ 36quad_uart.v \ 37simple_uart.v \ 38simple_uart_tx.v \ 39simple_uart_rx.v \ 40oneshot_2clk.v \ 41sd_spi.v \ 42sd_spi_wb.v \ 43wb_bridge_16_32.v \ 44reset_sync.v \ 45priority_enc.v \ 46pic.v \ 47longfifo.v \ 48shortfifo.v \ 49medfifo.v \ 50s3a_icap_wb.v \ 51bootram.v \ 52nsgpio16LE.v \ 53settings_bus_16LE.v \ 54atr_controller16.v \ 55fifo_to_wb.v \ 56gpio_atr.v \ 57user_settings.v \ 58settings_fifo_ctrl.v \ 59simple_spi_core.v \ 60simple_i2c_core.v \ 61)) 62