1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18 19module ram_2port_mixed_width 20 (input clk16, 21 input en16, 22 input we16, 23 input [10:0] addr16, 24 input [15:0] di16, 25 output [15:0] do16, 26 input clk32, 27 input en32, 28 input we32, 29 input [9:0] addr32, 30 input [31:0] di32, 31 output [31:0] do32); 32 33 wire en32a = en32 & ~addr32[9]; 34 wire en32b = en32 & addr32[9]; 35 wire en16a = en16 & ~addr16[10]; 36 wire en16b = en16 & addr16[10]; 37 38 wire [31:0] do32a, do32b; 39 wire [15:0] do16a, do16b; 40 41 assign do32 = addr32[9] ? do32b : do32a; 42 assign do16 = addr16[10] ? do16b : do16a; 43 44 RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), 45 .INIT_B(18'h00000), 46 .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" 47 .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion 48 .SRVAL_B(18'h00000), // Port B output value upon SSR assertion 49 .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE 50 .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE 51 ) 52 RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output 53 .DOB(do16a), // Port B 16-bit Data Output 54 .DOPA(), // Port A 4-bit Parity Output 55 .DOPB(), // Port B 2-bit Parity Output 56 .ADDRA(addr32[8:0]), // Port A 9-bit Address Input 57 .ADDRB(addr16[9:0]), // Port B 10-bit Address Input 58 .CLKA(clk32), // Port A 1-bit Clock 59 .CLKB(clk16), // Port B 1-bit Clock 60 .DIA(di32), // Port A 32-bit Data Input 61 .DIB(di16), // Port B 16-bit Data Input 62 .DIPA(0), // Port A 4-bit parity Input 63 .DIPB(0), // Port-B 2-bit parity Input 64 .ENA(en32a), // Port A 1-bit RAM Enable Input 65 .ENB(en16a), // Port B 1-bit RAM Enable Input 66 .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input 67 .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input 68 .WEA({4{we32}}), // Port A 4-bit Write Enable Input 69 .WEB({2{we16}}) // Port B 2-bit Write Enable Input 70 ); 71 72 RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), 73 .INIT_B(18'h00000), 74 .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" 75 .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion 76 .SRVAL_B(18'h00000), // Port B output value upon SSR assertion 77 .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE 78 .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE 79 ) 80 RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output 81 .DOB(do16b), // Port B 16-bit Data Output 82 .DOPA(), // Port A 4-bit Parity Output 83 .DOPB(), // Port B 2-bit Parity Output 84 .ADDRA(addr32[8:0]), // Port A 9-bit Address Input 85 .ADDRB(addr16[9:0]), // Port B 10-bit Address Input 86 .CLKA(clk32), // Port A 1-bit Clock 87 .CLKB(clk16), // Port B 1-bit Clock 88 .DIA(di32), // Port A 32-bit Data Input 89 .DIB(di16), // Port B 16-bit Data Input 90 .DIPA(0), // Port A 4-bit parity Input 91 .DIPB(0), // Port-B 2-bit parity Input 92 .ENA(en32b), // Port A 1-bit RAM Enable Input 93 .ENB(en16b), // Port B 1-bit RAM Enable Input 94 .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input 95 .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input 96 .WEA({4{we32}}), // Port A 4-bit Write Enable Input 97 .WEB({2{we16}}) // Port B 2-bit Write Enable Input 98 ); 99 100endmodule // ram_2port_mixed_width 101 102 103 104 105// ISE 10.1.03 chokes on the following 106 107/* 108 109 reg [31:0] ram [(1<<AWIDTH)-1:0]; 110 integer i; 111 initial 112 for(i=0;i<512;i=i+1) 113 ram[i] <= 32'b0; 114 115 always @(posedge clk16) 116 if (en16) 117 begin 118 if (we16) 119 if(addr16[0]) 120 ram[addr16[10:1]][15:0] <= di16; 121 else 122 ram[addr16[10:1]][31:16] <= di16; 123 do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16]; 124 end 125 126 always @(posedge clk32) 127 if (en32) 128 begin 129 if (we32) 130 ram[addr32] <= di32; 131 do32 <= ram[addr32]; 132 end 133 134endmodule // ram_2port_mixed_width 135 136 137 */ 138