1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18 19// wb_bus_writer 20// 21// WB Bus Master device to send a sequence of single-word transactions 22// based on a list in a RAM or ROM (FASM interface) 23// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]} 24// continues until it gets an all-1s entry 25 26module wb_bus_writer (input start, 27 output done, 28 output reg [15:0] rom_addr, 29 input [47:0] rom_data, 30 // WB Master Interface, don't need wb_dat_i 31 input wb_clk_i, 32 input wb_rst_i, 33 output [31:0] wb_dat_o, 34 input wb_ack_i, 35 output [15:0] wb_adr_o, 36 output wb_cyc_o, 37 output [3:0] wb_sel_o, 38 output wb_stb_o, 39 output wb_we_o 40 ); 41 42`define IDLE 0 43`define READ 1 44 45 reg [3:0] state; 46 47 assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s 48 49 always @(posedge wb_clk_i) 50 if(wb_rst_i) 51 begin 52 rom_addr <= #1 0; 53 state <= #1 0; 54 end 55 else if(start) 56 begin 57 rom_addr <= #1 0; 58 state <= #1 `READ; 59 end 60 else if((state == `READ) && wb_ack_i) 61 if(done) 62 state <= #1 `IDLE; 63 else 64 rom_addr <= #1 rom_addr + 1; 65 66 assign wb_dat_o = rom_data[31:0]; 67 assign wb_adr_o = rom_data[47:32]; 68 assign wb_sel_o = 4'b1111; // All writes are the full 32 bits 69 70 assign wb_cyc_o = !done & (state != `IDLE); 71 assign wb_stb_o = !done & (state != `IDLE); 72 assign wb_we_o = !done & (state != `IDLE); 73 74endmodule // wb_bus_writer 75