1////////////////////////////////////////////////////////////////////// 2//// //// 3//// wb_master_model.v //// 4//// //// 5//// This file is part of the SPI IP core project //// 6//// http://www.opencores.org/projects/spi/ //// 7//// //// 8//// Author(s): //// 9//// - Simon Srot (simons@opencores.org) //// 10//// //// 11//// Based on: //// 12//// - i2c/bench/verilog/wb_master_model.v //// 13//// Copyright (C) 2001 Richard Herveille //// 14//// //// 15//// All additional information is avaliable in the Readme.txt //// 16//// file. //// 17//// //// 18////////////////////////////////////////////////////////////////////// 19//// //// 20//// Copyright (C) 2002 Authors //// 21//// //// 22//// This source file may be used and distributed without //// 23//// restriction provided that this copyright statement is not //// 24//// removed from the file and that any derivative work contains //// 25//// the original copyright notice and the associated disclaimer. //// 26//// //// 27//// This source file is free software; you can redistribute it //// 28//// and/or modify it under the terms of the GNU Lesser General //// 29//// Public License as published by the Free Software Foundation; //// 30//// either version 2.1 of the License, or (at your option) any //// 31//// later version. //// 32//// //// 33//// This source is distributed in the hope that it will be //// 34//// useful, but WITHOUT ANY WARRANTY; without even the implied //// 35//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 36//// PURPOSE. See the GNU Lesser General Public License for more //// 37//// details. //// 38//// //// 39//// You should have received a copy of the GNU Lesser General //// 40//// Public License along with this source; if not, download it //// 41//// from http://www.opencores.org/lgpl.shtml //// 42//// //// 43////////////////////////////////////////////////////////////////////// 44 45`include "timescale.v" 46 47module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); 48 49 parameter dwidth = 32; 50 parameter awidth = 32; 51 52 input clk, rst; 53 output [awidth -1:0] adr; 54 input [dwidth -1:0] din; 55 output [dwidth -1:0] dout; 56 output cyc, stb; 57 output we; 58 output [dwidth/8 -1:0] sel; 59 input ack, err, rty; 60 61 // Internal signals 62 reg [awidth -1:0] adr; 63 reg [dwidth -1:0] dout; 64 reg cyc, stb; 65 reg we; 66 reg [dwidth/8 -1:0] sel; 67 68 reg [dwidth -1:0] q; 69 70 // Memory Logic 71 initial 72 begin 73 adr = {awidth{1'bx}}; 74 dout = {dwidth{1'bx}}; 75 cyc = 1'b0; 76 stb = 1'bx; 77 we = 1'hx; 78 sel = {dwidth/8{1'bx}}; 79 #1; 80 end 81 82 // Wishbone write cycle 83 task wb_write; 84 input delay; 85 integer delay; 86 87 input [awidth -1:0] a; 88 input [dwidth -1:0] d; 89 90 begin 91 92 // wait initial delay 93 repeat(delay) @(posedge clk); 94 95 // assert wishbone signal 96 #1; 97 adr = a; 98 dout = d; 99 cyc = 1'b1; 100 stb = 1'b1; 101 we = 1'b1; 102 sel = {dwidth/8{1'b1}}; 103 @(posedge clk); 104 105 // wait for acknowledge from slave 106 while(~ack) @(posedge clk); 107 108 // negate wishbone signals 109 #1; 110 cyc = 1'b0; 111 stb = 1'bx; 112 adr = {awidth{1'bx}}; 113 dout = {dwidth{1'bx}}; 114 we = 1'hx; 115 sel = {dwidth/8{1'bx}}; 116 117 end 118 endtask 119 120 // Wishbone read cycle 121 task wb_read; 122 input delay; 123 integer delay; 124 125 input [awidth -1:0] a; 126 output [dwidth -1:0] d; 127 128 begin 129 130 // wait initial delay 131 repeat(delay) @(posedge clk); 132 133 // assert wishbone signals 134 #1; 135 adr = a; 136 dout = {dwidth{1'bx}}; 137 cyc = 1'b1; 138 stb = 1'b1; 139 we = 1'b0; 140 sel = {dwidth/8{1'b1}}; 141 @(posedge clk); 142 143 // wait for acknowledge from slave 144 while(~ack) @(posedge clk); 145 146 // negate wishbone signals 147 #1; 148 cyc = 1'b0; 149 stb = 1'bx; 150 adr = {awidth{1'bx}}; 151 dout = {dwidth{1'bx}}; 152 we = 1'hx; 153 sel = {dwidth/8{1'bx}}; 154 d = din; 155 156 end 157 endtask 158 159 // Wishbone compare cycle (read data from location and compare with expected data) 160 task wb_cmp; 161 input delay; 162 integer delay; 163 164 input [awidth -1:0] a; 165 input [dwidth -1:0] d_exp; 166 167 begin 168 wb_read (delay, a, q); 169 170 if (d_exp !== q) 171 $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); 172 end 173 endtask 174 175endmodule 176 177