1------------------------------------------------------------------------------- 2-- 3-- SD/MMC Bootloader 4-- Generic testbench element for a specific feature set 5-- 6-- $Id: tb_elem.vhd,v 1.7 2005/04/07 20:43:36 arniml Exp $ 7-- 8-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) 9-- 10-- All rights reserved, see COPYING. 11-- 12-- Redistribution and use in source and synthezised forms, with or without 13-- modification, are permitted provided that the following conditions are met: 14-- 15-- Redistributions of source code must retain the above copyright notice, 16-- this list of conditions and the following disclaimer. 17-- 18-- Redistributions in synthesized form must reproduce the above copyright 19-- notice, this list of conditions and the following disclaimer in the 20-- documentation and/or other materials provided with the distribution. 21-- 22-- Neither the name of the author nor the names of other contributors may 23-- be used to endorse or promote products derived from this software without 24-- specific prior written permission. 25-- 26-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36-- POSSIBILITY OF SUCH DAMAGE. 37-- 38-- Please report bugs to the author, but before you do so, please 39-- make sure that this is not a derivative work and that 40-- you have the latest version of this file. 41-- 42-- The latest version of this file can be found at: 43-- http://www.opencores.org/projects.cgi/web/spi_boot/overview 44-- 45------------------------------------------------------------------------------- 46 47library ieee; 48use ieee.std_logic_1164.all; 49 50 51entity tb_elem is 52 53 generic ( 54 chip_type_g : string := "none"; 55 has_sd_card_g : integer := 1 56 ); 57 port ( 58 clk_i : in std_logic; 59 reset_i : in std_logic; 60 eos_o : out boolean 61 ); 62 63end tb_elem; 64 65 66library ieee; 67use ieee.numeric_std.all; 68library std; 69use std.textio.all; 70 71use work.spi_boot_pack.all; 72use work.tb_pack.all; 73 74architecture behav of tb_elem is 75 76 component chip 77 port ( 78 clk_i : in std_logic; 79 reset_i : in std_logic; 80 set_sel_n_i : in std_logic_vector(3 downto 0); 81 spi_clk_o : out std_logic; 82 spi_cs_n_o : out std_logic; 83 spi_data_in_i : in std_logic; 84 spi_data_out_o : out std_logic; 85 start_i : in std_logic; 86 mode_i : in std_logic; 87 config_n_o : out std_logic; 88 detached_o : out std_logic; 89 cfg_init_n_i : in std_logic; 90 cfg_done_i : in std_logic; 91 dat_done_i : in std_logic; 92 cfg_clk_o : out std_logic; 93 cfg_dat_o : out std_logic 94 ); 95 end component; 96 97 component card 98 generic ( 99 card_type_g : string := "none"; 100 is_sd_card_g : integer := 1 101 ); 102 port ( 103 spi_clk_i : in std_logic; 104 spi_cs_n_i : in std_logic; 105 spi_data_i : in std_logic; 106 spi_data_o : out std_logic 107 ); 108 end component; 109 110 signal reset_s : std_logic; 111 112 -- SPI interface signals 113 signal spi_clk_s : std_logic; 114 signal spi_data_to_card_s : std_logic; 115 signal spi_data_from_card_s : std_logic; 116 signal spi_cs_n_s : std_logic; 117 118 -- config related signals 119 signal start_s : std_logic; 120 signal mode_s : std_logic; 121 signal config_n_s : std_logic; 122 signal cfg_init_n_s : std_logic; 123 signal cfg_done_s : std_logic; 124 signal dat_done_s : std_logic; 125 signal cfg_clk_s : std_logic; 126 signal cfg_dat_s : std_logic; 127 signal data_s : unsigned(7 downto 0); 128 129 signal set_sel_n_s : std_logic_vector(3 downto 0); 130 131 constant verbose_c : boolean := false; 132 133begin 134 135 -- weak pull-ups 136 spi_clk_s <= 'H'; 137 spi_cs_n_s <= 'H'; 138 spi_data_to_card_s <= 'H'; 139 140 ----------------------------------------------------------------------------- 141 -- DUT 142 ----------------------------------------------------------------------------- 143 dut_b : chip 144 port map ( 145 clk_i => clk_i, 146 reset_i => reset_s, 147 set_sel_n_i => set_sel_n_s, 148 spi_clk_o => spi_clk_s, 149 spi_cs_n_o => spi_cs_n_s, 150 spi_data_in_i => spi_data_from_card_s, 151 spi_data_out_o => spi_data_to_card_s, 152 start_i => start_s, 153 mode_i => mode_s, 154 config_n_o => config_n_s, 155 detached_o => open, 156 cfg_init_n_i => cfg_init_n_s, 157 cfg_done_i => cfg_done_s, 158 dat_done_i => dat_done_s, 159 cfg_clk_o => cfg_clk_s, 160 cfg_dat_o => cfg_dat_s 161 ); 162 163 card_b : card 164 generic map ( 165 card_type_g => chip_type_g, 166 is_sd_card_g => has_sd_card_g 167 ) 168 port map ( 169 spi_clk_i => spi_clk_s, 170 spi_cs_n_i => spi_cs_n_s, 171 spi_data_i => spi_data_to_card_s, 172 spi_data_o => spi_data_from_card_s 173 ); 174 175 176 ----------------------------------------------------------------------------- 177 -- DUT Stimuli 178 -- 179 stim: process 180 181 procedure rise_cfg_clk(num : integer) is 182 begin 183 for i in 1 to num loop 184 wait until cfg_clk_s'event and cfg_clk_s = '1'; 185 end loop; 186 end rise_cfg_clk; 187 188-- procedure fall_cfg_clk(num : integer) is 189-- begin 190-- for i in 1 to num loop 191-- wait until cfg_clk_s'event and cfg_clk_s = '0'; 192-- end loop; 193-- end fall_cfg_clk; 194 195 procedure rise_clk(num : integer) is 196 begin 197 for i in 1 to num loop 198 wait until clk_i'event and clk_i = '1'; 199 end loop; 200 end rise_clk; 201 202 procedure read_check_byte(ref : unsigned(7 downto 0)) is 203 variable byte_v : unsigned(7 downto 0); 204 variable dump_line : line; 205 begin 206 for bit in 7 downto 0 loop 207 rise_cfg_clk(1); 208 byte_v(bit) := cfg_dat_s; 209 end loop; 210 data_s <= byte_v; 211 212 if byte_v /= ref then 213 write(dump_line, chip_type_g); 214 write(dump_line, string'(" at ")); 215 write(dump_line, now); 216 write(dump_line, string'(": read_check_byte failed ")); 217 write(dump_line, to_integer(byte_v)); 218 write(dump_line, string'(" ")); 219 write(dump_line, to_integer(ref)); 220 writeline(output, dump_line); 221 end if; 222 end read_check_byte; 223 224 variable dump_line : line; 225 variable addr_v : unsigned(31 downto 0); 226 variable temp_v : unsigned( 7 downto 0); 227 variable set_sel_v : unsigned(3 downto 0); 228 229 begin 230 -- default assignments 231 -- these defaults show the required pull resistors 232 -- except start_i as this must be pulled high for automatic start 233 start_s <= '0'; 234 mode_s <= '1'; 235 cfg_init_n_s <= '1'; 236 cfg_done_s <= '0'; 237 dat_done_s <= '1'; 238 data_s <= (others => '1'); 239 addr_v := (others => '0'); 240 eos_o <= false; 241 set_sel_n_s <= (others => '1'); 242 reset_s <= '0'; 243 244 -- loop through some sets 245 for set in 0 to 3 loop 246 set_sel_v := to_unsigned(set, 4); 247 addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g 248 -- plus width_img_cnt_g 249 set_sel_n_s <= not std_logic_vector(set_sel_v); 250 251 assert not verbose_c 252 report chip_type_g & ": Processing set " & to_string(set) 253 severity note; 254 255 wait for 100 us; 256 reset_s <= '1'; 257 258 assert not verbose_c 259 report chip_type_g & ": Requesting image 0" 260 severity note; 261 262 -- signal start 263 start_s <= '1'; 264 mode_s <= '1'; 265 cfg_done_s <= '0'; 266 addr_v(19 downto 0) := (others => '0'); 267 wait until config_n_s = '0'; 268 -- run through configuration sequence 269 rise_clk(1); 270 cfg_init_n_s <= '0'; 271 rise_clk(3); 272 cfg_init_n_s <= '1'; 273 274 -- and receive 32 bytes from image 0 275 for i in 1 to 32 loop 276 temp_v := addr_v(0) & calc_crc(addr_v); 277 read_check_byte(temp_v); 278 addr_v := addr_v + 1; 279 end loop; 280 start_s <= '0'; 281 cfg_done_s <= '1'; 282 283 rise_clk(10); 284 285 assert not verbose_c 286 report chip_type_g & ": Requesting image 1" 287 severity note; 288 289 -- request next image 290 mode_s <= '0'; 291 start_s <= '1'; 292 addr_v(17 downto 0) := (others => '0'); 293 addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd 294 dat_done_s <= '0'; 295 296 -- receive another 32 bytes from image 1 297 for i in 1 to 32 loop 298 temp_v := addr_v(0) & calc_crc(addr_v); 299 read_check_byte(temp_v); 300 addr_v := addr_v + 1; 301 end loop; 302 start_s <= '0'; 303 dat_done_s <= '1'; 304 305 306 rise_clk(10); 307 308 assert not verbose_c 309 report chip_type_g & ": Requesting image 2" 310 severity note; 311 312 -- request next image 313 mode_s <= '1'; 314 start_s <= '1'; 315 addr_v(17 downto 0) := (others => '0'); 316 addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd 317 318 wait until config_n_s = '0'; 319 -- run through configuration sequence 320 rise_clk(1); 321 cfg_done_s <= '0'; 322 cfg_init_n_s <= '0'; 323 rise_clk(3); 324 cfg_init_n_s <= '1'; 325 326 -- receive another 32 bytes from image 2 327 for i in 1 to 32 loop 328 temp_v := addr_v(0) & calc_crc(addr_v); 329 read_check_byte(temp_v); 330 addr_v := addr_v + 1; 331 end loop; 332 start_s <= '0'; 333 cfg_done_s <= '1'; 334 335 -- give dut a chance to stop current transfer 336 wait until spi_cs_n_s = '1'; 337 rise_clk(10); 338 339 reset_s <= '0'; 340 end loop; 341 342 eos_o <= true; 343 wait; 344 end process stim; 345 -- 346 ----------------------------------------------------------------------------- 347 348end behav; 349 350 351------------------------------------------------------------------------------- 352-- File History: 353-- 354-- $Log: tb_elem.vhd,v $ 355-- Revision 1.7 2005/04/07 20:43:36 arniml 356-- add new port detached_o 357-- 358-- Revision 1.6 2005/03/09 19:48:04 arniml 359-- make verbosity level switchable 360-- 361-- Revision 1.5 2005/03/08 22:06:21 arniml 362-- added set selection 363-- 364-- Revision 1.4 2005/02/17 18:59:23 arniml 365-- clarify wording for images 366-- 367-- Revision 1.3 2005/02/16 19:34:56 arniml 368-- add weak pull-ups for SPI lines 369-- 370-- Revision 1.2 2005/02/13 17:14:03 arniml 371-- change dat_done handling 372-- 373-- Revision 1.1 2005/02/08 21:09:20 arniml 374-- initial check-in 375-- 376------------------------------------------------------------------------------- 377