1//
2// Copyright 2011 Ettus Research LLC
3//
4// This program is free software: you can redistribute it and/or modify
5// it under the terms of the GNU General Public License as published by
6// the Free Software Foundation, either version 3 of the License, or
7// (at your option) any later version.
8//
9// This program is distributed in the hope that it will be useful,
10// but WITHOUT ANY WARRANTY; without even the implied warranty of
11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12// GNU General Public License for more details.
13//
14// You should have received a copy of the GNU General Public License
15// along with this program.  If not, see <http://www.gnu.org/licenses/>.
16//
17
18
19// TX side of flow control -- when other side sends PAUSE, we wait
20
21module flow_ctrl_tx
22  (input        rst,
23   input        tx_clk,
24   //host processor
25   input        tx_pause_en,
26   // From MAC_rx_ctrl
27   input [15:0] pause_quanta,
28   input        pause_quanta_val,
29   // MAC_tx_ctrl
30   output       pause_apply,
31   input        paused);
32
33   // ******************************************************************************
34   // Inhibit our TX from transmitting because they sent us a PAUSE frame
35   // ******************************************************************************
36
37   // Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be
38   //   as big as 16 bits, so 22 bits are needed for the counter
39
40   reg [15+6:0] pause_quanta_counter;
41   reg 		pqval_d1, pqval_d2;
42
43   always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
44   always @(posedge tx_clk) pqval_d2 <= pqval_d1;
45
46   always @ (posedge tx_clk or posedge rst)
47     if (rst)
48       pause_quanta_counter <= 0;
49     else if (pqval_d1 & ~pqval_d2)
50       pause_quanta_counter <= {pause_quanta, 6'b0};
51     else if((pause_quanta_counter!=0) & paused)
52       pause_quanta_counter <= pause_quanta_counter - 1;
53
54   assign	pause_apply = tx_pause_en & (pause_quanta_counter != 0);
55
56endmodule // flow_ctrl
57