1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18 19module simple_gemac_wrapper 20 #(parameter RXFIFOSIZE=9, 21 parameter TXFIFOSIZE=9, 22 parameter RX_FLOW_CTRL=0) 23 (input clk125, input reset, 24 // GMII 25 output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, 26 input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, 27 28 // Client FIFO Interfaces 29 input sys_clk, 30 output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, 31 input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, 32 33 // Wishbone Interface 34 input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, 35 input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, 36 37 // MIIM 38 inout mdio, output mdc, 39 output [31:0] debug); 40 41 wire clear = 0; 42 wire [7:0] rx_data, tx_data; 43 wire tx_clk, tx_valid, tx_error, tx_ack; 44 wire rx_clk, rx_valid, rx_error, rx_ack; 45 46 wire [47:0] ucast_addr, mcast_addr; 47 wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all; 48 wire pause_req; 49 wire pause_request_en, pause_respect_en; 50 wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; 51 52 wire [31:0] debug_state; 53 54 wire tx_reset, rx_reset; 55 reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset)); 56 reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset)); 57 58 simple_gemac simple_gemac 59 (.clk125(clk125), .reset(reset), 60 .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), 61 .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), 62 .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), 63 .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), 64 .pause_req(RX_FLOW_CTRL ? pause_req : 1'b0), .pause_time_req(RX_FLOW_CTRL ? pause_time_req : 16'd0), 65 .pause_respect_en(pause_respect_en), 66 .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), 67 .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 68 .pass_pause(pass_pause), .pass_all(pass_all), 69 .rx_clk(rx_clk), .rx_data(rx_data), 70 .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), 71 .tx_clk(tx_clk), .tx_data(tx_data), 72 .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack), 73 .debug(debug_state) 74 ); 75 76 simple_gemac_wb simple_gemac_wb 77 (.wb_clk(wb_clk), .wb_rst(wb_rst), 78 .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we), 79 .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), 80 .mdio(mdio), .mdc(mdc), 81 .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), 82 .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 83 .pass_pause(pass_pause), .pass_all(pass_all), 84 .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en), 85 .pause_time(pause_time), .pause_thresh(pause_thresh) ); 86 87 // RX FIFO Chain 88 wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; 89 wire [7:0] rx_ll_data; 90 91 wire [18:0] rx_f19_data_int1, rx_f19_data_int2; 92 wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2; 93 wire [35:0] rx_f36_data_int; 94 wire rx_f36_src_rdy_int, rx_f36_dst_rdy_int; 95 96 rxmac_to_ll8 rx_adapt 97 (.clk(rx_clk), .reset(rx_reset), .clear(0), 98 .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), 99 .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof 100 .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); 101 102 ll8_to_fifo19 ll8_to_fifo19 103 (.clk(rx_clk), .reset(rx_reset), .clear(0), 104 .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), 105 .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy), 106 .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1)); 107 108 fifo19_rxrealign fifo19_rxrealign 109 (.clk(rx_clk), .reset(rx_reset), .clear(0), 110 .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), 111 .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) ); 112 113 fifo19_to_fifo36 rx_fifo19_to_fifo36 114 (.clk(rx_clk), .reset(rx_reset), .clear(0), 115 .f19_datain(rx_f19_data_int2), .f19_src_rdy_i(rx_f19_src_rdy_int2), .f19_dst_rdy_o(rx_f19_dst_rdy_int2), 116 .f36_dataout(rx_f36_data_int), .f36_src_rdy_o(rx_f36_src_rdy_int), .f36_dst_rdy_i(rx_f36_dst_rdy_int) ); 117 118 fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo 119 (.wclk(rx_clk), .datain(rx_f36_data_int), 120 .src_rdy_i(rx_f36_src_rdy_int), .dst_rdy_o(rx_f36_dst_rdy_int), .space(rx_fifo_space), 121 .rclk(sys_clk), .dataout(rx_f36_data), 122 .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset)); 123 124 // TX FIFO Chain 125 wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; 126 wire [7:0] tx_ll_data; 127 wire [35:0] tx_f36_data_int1, tx_f36_data_int2; 128 wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_src_rdy_int2, tx_f36_dst_rdy_int2; 129 130 fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo 131 (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), 132 .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), 133 .arst(reset)); 134 135 ethtx_realign ethtx_realign 136 (.clk(tx_clk), .reset(tx_reset), .clear(clear), 137 .datain(tx_f36_data_int1), .src_rdy_i(tx_f36_src_rdy_int1), .dst_rdy_o(tx_f36_dst_rdy_int1), 138 .dataout(tx_f36_data_int2), .src_rdy_o(tx_f36_src_rdy_int2), .dst_rdy_i(tx_f36_dst_rdy_int2) ); 139 140 fifo36_to_ll8 fifo36_to_ll8 141 (.clk(tx_clk), .reset(tx_reset), .clear(clear), 142 .f36_data(tx_f36_data_int2), .f36_src_rdy_i(tx_f36_src_rdy_int2), .f36_dst_rdy_o(tx_f36_dst_rdy_int2), 143 .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), 144 .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy)); 145 146 ll8_to_txmac ll8_to_txmac 147 (.clk(tx_clk), .reset(tx_reset), .clear(clear), 148 .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), 149 .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), 150 .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); 151 152 // Flow Control 153 generate 154 if(RX_FLOW_CTRL==1) 155 flow_ctrl_rx flow_ctrl_rx 156 (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh), 157 .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space), 158 .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req)); 159 endgenerate 160 161 wire [31:0] debug_tx, debug_rx; 162 163 assign debug_tx = { { tx_ll_data }, 164 { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 4'b0 }, 165 { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, 166 { tx_data} }; 167 assign debug_rx = { { rx_ll_data }, 168 { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 }, 169 { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int, rx_f36_dst_rdy_int, rx_f36_data_int[34:32]}, 170 { rx_data} }; 171 172 assign debug = debug_rx; 173 174endmodule // simple_gemac_wrapper 175 176