1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18 19module udp_wrapper 20 #(parameter BASE=0) 21 (input clk, input reset, input clear, 22 input set_stb, input [7:0] set_addr, input [31:0] set_data, 23 input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o, 24 output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i, 25 26 output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i, 27 input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o, 28 output [31:0] debug 29 ); 30 31 wire tx_int1_src_rdy, tx_int1_dst_rdy; 32 wire [18:0] tx_int1_data; 33 34 wire tx_int2_src_rdy, tx_int2_dst_rdy; 35 wire [18:0] tx_int2_data; 36 wire [31:0] debug_state; 37 38 // TX side 39 fifo36_to_fifo19 fifo36_to_fifo19 40 (.clk(clk), .reset(reset), .clear(clear), 41 .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o), 42 .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) ); 43 44 fifo_short #(.WIDTH(19)) shortfifo19_a 45 (.clk(clk), .reset(reset), .clear(clear), 46 .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy), 47 .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy), 48 .space(), .occupied() ); 49 50 prot_eng_tx #(.BASE(BASE)) prot_eng_tx 51 (.clk(clk), .reset(reset), .clear(clear), 52 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 53 .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy), 54 .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) ); 55 56 // RX side 57 wire rx_int1_src_rdy, rx_int1_dst_rdy; 58 wire [18:0] rx_int1_data; 59 60 wire rx_int2_src_rdy, rx_int2_dst_rdy; 61 wire [18:0] rx_int2_data; 62 63 //wire rx_int3_src_rdy, rx_int3_dst_rdy; 64 //wire [35:0] rx_int3_data; 65 66`ifdef USE_PROT_ENG 67 prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx 68 (.clk(clk), .reset(reset), .clear(clear), 69 .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o), 70 .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) ); 71`else 72 fifo19_rxrealign fifo19_rxrealign 73 (.clk(clk), .reset(reset), .clear(clear), 74 .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o), 75 .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) ); 76`endif // !`ifdef USE_PROT_ENG 77 78 fifo_short #(.WIDTH(19)) shortfifo19_b 79 (.clk(clk), .reset(reset), .clear(clear), 80 .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy), 81 .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy), 82 .space(), .occupied() ); 83 84 fifo19_to_fifo36 fifo19_to_fifo36 85 (.clk(clk), .reset(reset), .clear(clear), 86 .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy), 87 .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i), 88 .debug(debug_state)); 89 90 /* 91 fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo 92 (.clk(clk), .reset(reset), .clear(clear), 93 .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), 94 .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), 95 .space(), .occupied() ); 96*/ 97 /* 98 assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, 99 { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, 100 { rx_int3_data[35:32], rx_f36_data[35:32] }, 101 { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } }; 102 */ 103 104 assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] }, 105 { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] }, 106 { tx_int2_data[15:8] }, 107 { tx_int2_data[7:0] } }; 108 109endmodule // udp_wrapper 110