1// 2// Copyright 2015 Ettus Research, a National Instruments Company 3// 4// SPDX-License-Identifier: LGPL-3.0-or-later 5// 6 7// 8// There are various obligations put on this code not present in regular BRAM based FIFO's 9// 10// 1) Bursts are way more efficient, use local small FIFO's to interact with DRAM 11// 2) Never cross a 4KByte address boundary within a single transaction, this is an AXI4 rule. 12// 3) 2^SIZE must be greater than 4KB so that the 4KByte page protection also deals with FIFO wrap corner case. 13// 14module axi_dma_fifo 15#( 16 parameter SIMULATION = 0, // Shorten flush counter for simulation 17 parameter DEFAULT_BASE = 30'h00000000, 18 parameter DEFAULT_MASK = 30'hFF000000, 19 parameter DEFAULT_TIMEOUT = 12'd256, 20 parameter BUS_CLK_RATE = 32'd166666666, // Frequency in Hz of bus_clk 21 parameter SR_BASE = 0, // Base address for settings registers 22 parameter EXT_BIST = 0, // If 1 then instantiate extended BIST with dynamic SID, delays and BW counters 23 parameter MAX_PKT_LEN = 12 // Log2 of maximum packet length 24) ( 25 input bus_clk, 26 input bus_reset, 27 input dram_clk, 28 input dram_reset, 29 // 30 // AXI Write address channel 31 // 32 output [0 : 0] m_axi_awid, // Write address ID. This signal is the identification tag for the write address signals 33 output [31 : 0] m_axi_awaddr, // Write address. The write address gives the address of the first transfer in a write burst 34 output [7 : 0] m_axi_awlen, // Burst length. The burst length gives the exact number of transfers in a burst. 35 output [2 : 0] m_axi_awsize, // Burst size. This signal indicates the size of each transfer in the burst. 36 output [1 : 0] m_axi_awburst, // Burst type. The burst type and the size information, determine how the address is calculated 37 output [0 : 0] m_axi_awlock, // Lock type. Provides additional information about the atomic characteristics of the transfer. 38 output [3 : 0] m_axi_awcache, // Memory type. This signal indicates how transactions are required to progress 39 output [2 : 0] m_axi_awprot, // Protection type. This signal indicates the privilege and security level of the transaction 40 output [3 : 0] m_axi_awqos, // Quality of Service, QoS. The QoS identifier sent for each write transaction 41 output [3 : 0] m_axi_awregion, // Region identifier. Permits a single physical interface on a slave to be re-used. 42 output [0 : 0] m_axi_awuser, // User signal. Optional User-defined signal in the write address channel. 43 output m_axi_awvalid, // Write address valid. This signal indicates that the channel is signaling valid write addr 44 input m_axi_awready, // Write address ready. This signal indicates that the slave is ready to accept an address 45 // 46 // AXI Write data channel. 47 // 48 output [63 : 0] m_axi_wdata, // Write data 49 output [7 : 0] m_axi_wstrb, // Write strobes. This signal indicates which byte lanes hold valid data. 50 output m_axi_wlast, // Write last. This signal indicates the last transfer in a write burst 51 output [0 : 0] m_axi_wuser, // User signal. Optional User-defined signal in the write data channel. 52 output m_axi_wvalid, // Write valid. This signal indicates that valid write data and strobes are available. 53 input m_axi_wready, // Write ready. This signal indicates that the slave can accept the write data. 54 // 55 // AXI Write response channel signals 56 // 57 input [0 : 0] m_axi_bid, // Response ID tag. This signal is the ID tag of the write response. 58 input [1 : 0] m_axi_bresp, // Write response. This signal indicates the status of the write transaction. 59 input [0 : 0] m_axi_buser, // User signal. Optional User-defined signal in the write response channel. 60 input m_axi_bvalid, // Write response valid. This signal indicates that the channel is signaling a valid response 61 output m_axi_bready, // Response ready. This signal indicates that the master can accept a write response 62 // 63 // AXI Read address channel 64 // 65 output [0 : 0] m_axi_arid, // Read address ID. This signal is the identification tag for the read address group of signals 66 output [31 : 0] m_axi_araddr, // Read address. The read address gives the address of the first transfer in a read burst 67 output [7 : 0] m_axi_arlen, // Burst length. This signal indicates the exact number of transfers in a burst. 68 output [2 : 0] m_axi_arsize, // Burst size. This signal indicates the size of each transfer in the burst. 69 output [1 : 0] m_axi_arburst, // Burst type. The burst type and the size information determine how the address for each transfer 70 output [0 : 0] m_axi_arlock, // Lock type. This signal provides additional information about the atomic characteristics 71 output [3 : 0] m_axi_arcache, // Memory type. This signal indicates how transactions are required to progress 72 output [2 : 0] m_axi_arprot, // Protection type. This signal indicates the privilege and security level of the transaction 73 output [3 : 0] m_axi_arqos, // Quality of Service, QoS. QoS identifier sent for each read transaction. 74 output [3 : 0] m_axi_arregion, // Region identifier. Permits a single physical interface on a slave to be re-used 75 output [0 : 0] m_axi_aruser, // User signal. Optional User-defined signal in the read address channel. 76 output m_axi_arvalid, // Read address valid. This signal indicates that the channel is signaling valid read addr 77 input m_axi_arready, // Read address ready. This signal indicates that the slave is ready to accept an address 78 // 79 // AXI Read data channel 80 // 81 input [0 : 0] m_axi_rid, // Read ID tag. This signal is the identification tag for the read data group of signals 82 input [63 : 0] m_axi_rdata, // Read data. 83 input [1 : 0] m_axi_rresp, // Read response. This signal indicates the status of the read transfer 84 input m_axi_rlast, // Read last. This signal indicates the last transfer in a read burst. 85 input [0 : 0] m_axi_ruser, // User signal. Optional User-defined signal in the read data channel. 86 input m_axi_rvalid, // Read valid. This signal indicates that the channel is signaling the required read data. 87 output m_axi_rready, // Read ready. This signal indicates that the master can accept the read data and response 88 // 89 // CHDR friendly AXI stream input 90 // 91 input [63:0] i_tdata, 92 input i_tlast, 93 input i_tvalid, 94 output i_tready, 95 // 96 // CHDR friendly AXI Stream output 97 // 98 output [63:0] o_tdata, 99 output o_tlast, 100 output o_tvalid, 101 input o_tready, 102 // 103 // Settings and Readback 104 // 105 input set_stb, 106 input [7:0] set_addr, 107 input [31:0] set_data, 108 output reg [31:0] rb_data, 109 // 110 // Debug Bus 111 // 112 output [197:0] debug 113); 114 115 // 116 // We are only solving for width 64bits here, since it's our standard CHDR quanta 117 // 118 localparam DWIDTH = 64; 119 localparam AWIDTH = 30; //Can address 1GiB of memory 120 121 // 122 // Settings and Readback 123 // 124 wire [2:0] rb_addr; 125 wire clear_bclk, flush_bclk; 126 wire supress_enable_bclk; 127 wire [15:0] supress_threshold_bclk; 128 wire [11:0] timeout_bclk; 129 wire [AWIDTH-1:0] fifo_base_addr_bclk; 130 wire [AWIDTH-1:0] fifo_addr_mask_bclk; 131 wire [0:0] ctrl_reserved; 132 133 wire [31:0] rb_fifo_status; 134 wire [3:0] rb_bist_status; 135 wire [95:0] rb_bist_bw_ratio; 136 reg [31:0] out_pkt_count = 32'd0; 137 138 localparam RB_FIFO_STATUS = 3'd0; 139 localparam RB_BIST_STATUS = 3'd1; 140 localparam RB_BIST_XFER_CNT = 3'd2; 141 localparam RB_BIST_CYC_CNT = 3'd3; 142 localparam RB_BUS_CLK_RATE = 3'd4; 143 localparam RB_OUT_PKT_CNT = 3'd5; 144 145 // SETTING: Readback Address Register 146 // Fields: 147 // - [2:0] : Address for readback register 148 // - 0 = RB_FIFO_STATUS 149 // - 1 = RB_BIST_STATUS 150 // - 2 = RB_BIST_XFER_CNT 151 // - 3 = RB_BIST_CYC_CNT 152 // - 4 = RB_BUS_CLK_RATE 153 // - rest reserved 154 setting_reg #(.my_addr(SR_BASE + 0), .awidth(8), .width(3), .at_reset(3'b000)) sr_readback 155 (.clk(bus_clk), .rst(bus_reset), 156 .strobe(set_stb), .addr(set_addr), .in(set_data), 157 .out(rb_addr), .changed()); 158 159 // SETTING: FIFO Control Register 160 // Fields: 161 // - [0] : Clear FIFO and discard stored data 162 // - [1] : Enable read suppression to prioritize writes 163 // - [2] : Flush all packets from the FIFO 164 // - [3] : Reserved 165 // - [15:4] : Timeout (in memory clock beats) for issuing smaller than optimal bursts 166 // - [31:16] : Read suppression threshold in number of words 167 setting_reg #(.my_addr(SR_BASE + 1), .awidth(8), .width(32), .at_reset({16'h0, DEFAULT_TIMEOUT[11:0], 1'b0, 1'b0, 1'b0, 1'b1})) sr_fifo_ctrl 168 (.clk(bus_clk), .rst(bus_reset), 169 .strobe(set_stb), .addr(set_addr), .in(set_data), 170 .out({supress_threshold_bclk, timeout_bclk, ctrl_reserved, flush_bclk, supress_enable_bclk, clear_bclk}), .changed()); 171 172 // SETTING: Base Address for FIFO in memory space 173 // Fields: 174 // - [29:0] : Base address 175 setting_reg #(.my_addr(SR_BASE + 2), .awidth(8), .width(AWIDTH), .at_reset(DEFAULT_BASE)) sr_fifo_base_addr 176 (.clk(bus_clk), .rst(bus_reset), 177 .strobe(set_stb), .addr(set_addr), .in(set_data), 178 .out(fifo_base_addr_bclk), .changed()); 179 180 // SETTING: Address Mask for FIFO in memory space. The mask is ANDed with the base address to define 181 // a unique address for this FIFO. A zero in the mask signifies that the DRAM FIFO can 182 // utilize the address bit internally for maintaining FIFO data 183 // Fields: 184 // - [29:0] : Address mask 185 setting_reg #(.my_addr(SR_BASE + 3), .awidth(8), .width(AWIDTH), .at_reset(DEFAULT_MASK)) sr_fifo_addr_mask 186 (.clk(bus_clk), .rst(bus_reset), 187 .strobe(set_stb), .addr(set_addr), .in(set_data), 188 .out(fifo_addr_mask_bclk), .changed()); 189 190 always @(*) begin 191 case(rb_addr) 192 RB_FIFO_STATUS: rb_data = rb_fifo_status; 193 RB_BIST_STATUS: rb_data = {(EXT_BIST?1'b1:1'b0), 27'h0, rb_bist_status}; 194 RB_BIST_XFER_CNT: rb_data = rb_bist_bw_ratio[79:48]; 195 RB_BIST_CYC_CNT: rb_data = rb_bist_bw_ratio[31:0]; 196 RB_BUS_CLK_RATE: rb_data = BUS_CLK_RATE; 197 RB_OUT_PKT_CNT: rb_data = out_pkt_count; 198 default: rb_data = 32'h0; 199 endcase 200 end 201 202 // 203 // Synchronize settings register values to dram_clk 204 // 205 wire clear; 206 synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_inst (.clk(dram_clk), .rst(1'b0), .in(clear_bclk), .out(clear)); 207 208 wire set_suppress_en; 209 wire [15:0] set_supress_threshold; 210 wire [11:0] set_timeout; 211 wire [AWIDTH-1:0] set_fifo_base_addr, set_fifo_addr_mask, set_fifo_addr_mask_bar; 212 213 wire [(72-AWIDTH-29-1):0] set_sync_discard0; 214 wire [(72-(2*AWIDTH)-1):0] set_sync_discard1; 215 fifo_short_2clk set_sync_fifo0( 216 .rst(bus_reset), 217 .wr_clk(bus_clk), .din({{(72-AWIDTH-29){1'b0}}, timeout_bclk, supress_enable_bclk, supress_threshold_bclk, fifo_base_addr_bclk}), 218 .wr_en(1'b1), .full(), .wr_data_count(), 219 .rd_clk(dram_clk), .dout({set_sync_discard0, set_timeout, set_suppress_en, set_supress_threshold, set_fifo_base_addr}), 220 .rd_en(1'b1), .empty(), .rd_data_count() 221 ); 222 fifo_short_2clk set_sync_fifo1( 223 .rst(bus_reset), 224 .wr_clk(bus_clk), .din({{(72-(2*AWIDTH)){1'b0}}, ~fifo_addr_mask_bclk, fifo_addr_mask_bclk}), 225 .wr_en(1'b1), .full(), .wr_data_count(), 226 .rd_clk(dram_clk), .dout({set_sync_discard1, set_fifo_addr_mask_bar, set_fifo_addr_mask}), 227 .rd_en(1'b1), .empty(), .rd_data_count() 228 ); 229 230 // 231 // Input side declarations 232 // 233 localparam [2:0] INPUT_IDLE = 0; 234 localparam [2:0] INPUT1 = 1; 235 localparam [2:0] INPUT2 = 2; 236 localparam [2:0] INPUT3 = 3; 237 localparam [2:0] INPUT4 = 4; 238 localparam [2:0] INPUT5 = 5; 239 localparam [2:0] INPUT6 = 6; 240 241 reg [2:0] input_state; 242 reg input_timeout_triggered; 243 reg input_timeout_reset; 244 reg [8:0] input_timeout_count; 245 reg [AWIDTH-1:0] write_addr; 246 reg write_ctrl_valid; 247 wire write_ctrl_ready; 248 reg [7:0] write_count = 8'd0; 249 reg [8:0] write_count_plus_one = 9'd1; // Maintain a +1 version to break critical timing paths 250 reg update_write; 251 252 // 253 // Output side declarations 254 // 255 localparam [2:0] OUTPUT_IDLE = 0; 256 localparam [2:0] OUTPUT1 = 1; 257 localparam [2:0] OUTPUT2 = 2; 258 localparam [2:0] OUTPUT3 = 3; 259 localparam [2:0] OUTPUT4 = 4; 260 localparam [2:0] OUTPUT5 = 5; 261 localparam [2:0] OUTPUT6 = 6; 262 263 reg [2:0] output_state; 264 reg output_timeout_triggered; 265 reg output_timeout_reset; 266 reg [8:0] output_timeout_count; 267 reg [AWIDTH-1:0] read_addr; 268 reg read_ctrl_valid; 269 wire read_ctrl_ready; 270 reg [7:0] read_count = 8'd0; 271 reg [8:0] read_count_plus_one = 9'd1; // Maintain a +1 version to break critical timing paths 272 reg update_read; 273 274 // Track main FIFO active size. 275 reg [AWIDTH-3:0] space, occupied, occupied_minus_one; // Maintain a -1 version to break critical timing paths 276 reg [AWIDTH-3:0] input_page_boundry, output_page_boundry; // Cache in a register to break critical timing paths 277 278 // Assign FIFO status bits 279 wire [71:0] status_out_bclk; 280 fifo_short_2clk status_fifo_2clk( 281 .rst(dram_reset), 282 .wr_clk(dram_clk), .din({{(72-(AWIDTH-2)){1'b0}}, occupied}), 283 .wr_en(1'b1), .full(), .wr_data_count(), 284 .rd_clk(bus_clk), .dout(status_out_bclk), 285 .rd_en(1'b1), .empty(), .rd_data_count() 286 ); 287 assign rb_fifo_status[31] = 1'b1; //DRAM FIFO signature (validates existence of DRAM FIFO) 288 assign rb_fifo_status[30:27] = {o_tvalid, o_tready, i_tvalid, i_tready}; //Ready valid flags 289 assign rb_fifo_status[26:0] = status_out_bclk[26:0]; //FIFO fullness count in 64bit words (max 27 bits = 1GiB) 290 291 /////////////////////////////////////////////////////////////////////////////// 292 // Inline BIST for production testing 293 // 294 wire i_tready_int; 295 296 wire [DWIDTH-1:0] i_tdata_fifo; 297 wire i_tvalid_fifo, i_tready_fifo, i_tlast_fifo; 298 299 wire [DWIDTH-1:0] i_tdata_bist; 300 wire i_tvalid_bist, i_tready_bist, i_tlast_bist; 301 302 wire [DWIDTH-1:0] o_tdata_int; 303 wire o_tvalid_int, o_tready_int, o_tlast_int; 304 305 wire [DWIDTH-1:0] o_tdata_fifo; 306 wire o_tvalid_fifo, o_tready_fifo, o_tlast_fifo; 307 308 wire [DWIDTH-1:0] o_tdata_bist; 309 wire o_tvalid_bist, o_tready_bist, o_tlast_bist; 310 311 wire [DWIDTH-1:0] o_tdata_gate; 312 wire o_tvalid_gate, o_tready_gate, o_tlast_gate; 313 314 axi_mux4 #(.PRIO(1), .WIDTH(DWIDTH), .BUFFER(1)) axi_mux ( 315 .clk(bus_clk), .reset(bus_reset), .clear(clear_bclk), 316 .i0_tdata(i_tdata), .i0_tlast(i_tlast), .i0_tvalid(i_tvalid), .i0_tready(i_tready_int), 317 .i1_tdata(i_tdata_bist), .i1_tlast(i_tlast_bist), .i1_tvalid(i_tvalid_bist), .i1_tready(i_tready_bist), 318 .i2_tdata({DWIDTH{1'b0}}), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(), 319 .i3_tdata({DWIDTH{1'b0}}), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(), 320 .o_tdata(i_tdata_fifo), .o_tlast(i_tlast_fifo), .o_tvalid(i_tvalid_fifo), .o_tready(i_tready_fifo) 321 ); 322 assign i_tready = i_tready_int & (~clear_bclk); 323 324 wire bist_running, bist_done; 325 wire [1:0] bist_error; 326 327 axi_chdr_test_pattern #( 328 .DELAY_MODE(EXT_BIST ? "DYNAMIC" : "STATIC"), 329 .SID_MODE(EXT_BIST ? "DYNAMIC" : "STATIC"), 330 .BW_COUNTER(EXT_BIST ? 1 : 0), 331 .SR_BASE(SR_BASE + 4) 332 ) axi_chdr_test_pattern_i ( 333 .clk(bus_clk), .reset(bus_reset | clear_bclk), 334 .i_tdata(i_tdata_bist), .i_tlast(i_tlast_bist), .i_tvalid(i_tvalid_bist), .i_tready(i_tready_bist), 335 .o_tdata(o_tdata_bist), .o_tlast(o_tlast_bist), .o_tvalid(o_tvalid_bist), .o_tready(o_tready_bist), 336 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 337 .running(bist_running), .done(bist_done), .error(bist_error), .status_vtr(), .bw_ratio(rb_bist_bw_ratio) 338 ); 339 assign rb_bist_status = {bist_error, bist_done, bist_running}; 340 341 axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(DWIDTH)) axi_demux( 342 .clk(bus_clk), .reset(bus_reset), .clear(clear_bclk), 343 .header(), .dest({1'b0, bist_running}), 344 .i_tdata(o_tdata_fifo), .i_tlast(o_tlast_fifo), .i_tvalid(o_tvalid_fifo), .i_tready(o_tready_fifo), 345 .o0_tdata(o_tdata_gate), .o0_tlast(o_tlast_gate), .o0_tvalid(o_tvalid_gate), .o0_tready(o_tready_gate), 346 .o1_tdata(o_tdata_bist), .o1_tlast(o_tlast_bist), .o1_tvalid(o_tvalid_bist), .o1_tready(o_tready_bist), 347 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0), 348 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0) 349 ); 350 351 //Insert package gate before output to absorb any intra-packet bubble cycles 352 axi_packet_gate #(.WIDTH(DWIDTH), .SIZE(MAX_PKT_LEN)) out_pkt_gate ( 353 .clk(bus_clk), .reset(bus_reset), .clear(clear_bclk), 354 .i_tdata(o_tdata_gate), .i_tlast(o_tlast_gate), .i_tvalid(o_tvalid_gate), .i_tready(o_tready_gate), 355 .i_terror(1'b0), 356 .o_tdata(o_tdata_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int) 357 ); 358 359 axis_packet_flush #( 360 .WIDTH(DWIDTH), .FLUSH_PARTIAL_PKTS(0), .TIMEOUT_W(1), .PIPELINE("NONE") 361 ) flusher_i ( 362 .clk(bus_clk), .reset(bus_reset), 363 .enable(clear_bclk | flush_bclk), .timeout(1'b0), .flushing(), .done(), 364 .s_axis_tdata(o_tdata_int), .s_axis_tlast(o_tlast_int), 365 .s_axis_tvalid(o_tvalid_int), .s_axis_tready(o_tready_int), 366 .m_axis_tdata(o_tdata), .m_axis_tlast(o_tlast), 367 .m_axis_tvalid(o_tvalid), .m_axis_tready(o_tready) 368 ); 369 370 always @(posedge bus_clk) begin 371 if (bus_reset) begin 372 out_pkt_count <= 32'd0; 373 end else if (o_tlast_int & o_tvalid_int & o_tready_int) begin 374 out_pkt_count <= out_pkt_count + 32'd1; 375 end 376 end 377 378 // 379 // Buffer input in FIFO's. Embeded tlast signal using ESCape code. 380 // 381 382 wire [DWIDTH-1:0] i_tdata_i0; 383 wire i_tvalid_i0, i_tready_i0, i_tlast_i0; 384 385 wire [DWIDTH-1:0] i_tdata_i1; 386 wire i_tvalid_i1, i_tready_i1, i_tlast_i1; 387 388 wire [DWIDTH-1:0] i_tdata_i2; 389 wire i_tvalid_i2, i_tready_i2; 390 391 wire [DWIDTH-1:0] i_tdata_i3; 392 wire i_tvalid_i3, i_tready_i3; 393 394 wire [DWIDTH-1:0] i_tdata_input; 395 wire i_tvalid_input, i_tready_input; 396 wire [15:0] space_input, occupied_input; 397 reg [15:0] space_input_reg; 398 reg supress_reads; 399 400 401 /////////////////////////////////////////////////////////////////////////////// 402 403 wire write_in, read_in, empty_in, full_in; 404 assign i_tready_fifo = ~full_in; 405 assign write_in = i_tvalid_fifo & i_tready_fifo; 406 assign i_tvalid_i0 = ~empty_in; 407 assign read_in = i_tvalid_i0 & i_tready_i0; 408 wire [6:0] discard_i0; 409 410 fifo_short_2clk fifo_short_2clk_i0 ( 411 .rst(bus_reset), 412 .wr_clk(bus_clk), 413 .din({7'h0,i_tlast_fifo,i_tdata_fifo}), // input [71 : 0] din 414 .wr_en(write_in), // input wr_en 415 .full(full_in), // output full 416 .wr_data_count(), // output [9 : 0] wr_data_count 417 418 .rd_clk(dram_clk), // input rd_clk 419 .dout({discard_i0,i_tlast_i0,i_tdata_i0}), // output [71 : 0] dout 420 .rd_en(read_in), // input rd_en 421 .empty(empty_in), // output empty 422 .rd_data_count() // output [9 : 0] rd_data_count 423 ); 424 425 axi_fifo_flop2 #(.WIDTH(DWIDTH+1)) input_pipe_i0 426 ( 427 .clk(dram_clk), 428 .reset(dram_reset), 429 .clear(clear), 430 // 431 .i_tdata({i_tlast_i0, i_tdata_i0}), 432 .i_tvalid(i_tvalid_i0), 433 .i_tready(i_tready_i0), 434 // 435 .o_tdata({i_tlast_i1, i_tdata_i1}), 436 .o_tvalid(i_tvalid_i1), 437 .o_tready(i_tready_i1) 438 ); 439 440 axi_embed_tlast #(.WIDTH(DWIDTH), .ADD_CHECKSUM(0)) axi_embed_tlast_i ( 441 .clk(dram_clk), 442 .reset(dram_reset), 443 .clear(clear), 444 // 445 .i_tdata(i_tdata_i1), 446 .i_tlast(i_tlast_i1), 447 .i_tvalid(i_tvalid_i1), 448 .i_tready(i_tready_i1), 449 // 450 .o_tdata(i_tdata_i2), 451 .o_tvalid(i_tvalid_i2), 452 .o_tready(i_tready_i2) 453 ); 454 455 axi_fifo_flop2 #(.WIDTH(DWIDTH)) input_pipe_i1 ( 456 .clk(dram_clk), 457 .reset(dram_reset), 458 .clear(clear), 459 // 460 .i_tdata(i_tdata_i2), 461 .i_tvalid(i_tvalid_i2), 462 .i_tready(i_tready_i2), 463 // 464 .o_tdata(i_tdata_i3), 465 .o_tvalid(i_tvalid_i3), 466 .o_tready(i_tready_i3) 467 ); 468 469 axi_fifo #(.WIDTH(DWIDTH),.SIZE(10)) fifo_i1 ( 470 .clk(dram_clk), 471 .reset(dram_reset), 472 .clear(clear), 473 // 474 .i_tdata(i_tdata_i3), 475 .i_tvalid(i_tvalid_i3), 476 .i_tready(i_tready_i3), 477 // 478 .o_tdata(i_tdata_input), 479 .o_tvalid(i_tvalid_input), 480 .o_tready(i_tready_input), 481 // 482 .space(space_input), 483 .occupied(occupied_input) 484 ); 485 486 // 487 // Monitor occupied_input to deduce when DRAM FIFO is running short of bandwidth and there is a danger of backpressure 488 // passing upstream of the DRAM FIFO. 489 // In this situation supress read requests to the DRAM FIFO so that more bandwidth is available to writes. 490 // 491 always @(posedge dram_clk) 492 begin 493 space_input_reg <= space_input; 494 if ((space_input_reg < set_supress_threshold[15:0]) && set_suppress_en) 495 supress_reads <= 1'b1; 496 else 497 supress_reads <= 1'b0; 498 end 499 500 // 501 // Buffer output in 32entry FIFO's. Extract embeded tlast signal. 502 // 503 wire [DWIDTH-1:0] o_tdata_output; 504 wire o_tvalid_output, o_tready_output; 505 wire [15:0] space_output, occupied_output; 506 507 wire [DWIDTH-1:0] o_tdata_i0; 508 wire o_tvalid_i0, o_tready_i0; 509 510 wire [DWIDTH-1:0] o_tdata_i1; 511 wire o_tvalid_i1, o_tready_i1; 512 513 wire [DWIDTH-1:0] o_tdata_i2; 514 wire o_tvalid_i2, o_tready_i2; 515 516 wire [DWIDTH-1:0] o_tdata_i3; 517 wire o_tvalid_i3, o_tready_i3; 518 519 wire [DWIDTH-1:0] o_tdata_i4; 520 wire o_tvalid_i4, o_tready_i4, o_tlast_i4; 521 522 wire [DWIDTH-1:0] o_tdata_i5; 523 wire o_tvalid_i5, o_tready_i5, o_tlast_i5; 524 525 wire checksum_error; 526 527 axi_fifo #(.WIDTH(DWIDTH),.SIZE(10)) fifo_i2 ( 528 .clk(dram_clk), 529 .reset(dram_reset), 530 .clear(clear), 531 // 532 .i_tdata(o_tdata_output), 533 .i_tvalid(o_tvalid_output), 534 .i_tready(o_tready_output), 535 // 536 .o_tdata(o_tdata_i0), 537 .o_tvalid(o_tvalid_i0), 538 .o_tready(o_tready_i0), 539 // 540 .space(space_output), 541 .occupied(occupied_output) 542 ); 543 544 // Place FLops straight after SRAM read access for timing. 545 axi_fifo_flop2 #(.WIDTH(DWIDTH)) output_pipe_i0 546 ( 547 .clk(dram_clk), 548 .reset(dram_reset), 549 .clear(clear), 550 // 551 .i_tdata(o_tdata_i0), 552 .i_tvalid(o_tvalid_i0), 553 .i_tready(o_tready_i0), 554 // 555 .o_tdata(o_tdata_i1), 556 .o_tvalid(o_tvalid_i1), 557 .o_tready(o_tready_i1 && ~supress_reads) 558 ); 559 560 // Read suppression logic 561 // The CL part of this exists between these 562 // axi_flops 563 axi_fifo_flop2 #(.WIDTH(DWIDTH)) output_pipe_i1 564 ( 565 .clk(dram_clk), 566 .reset(dram_reset), 567 .clear(clear), 568 // 569 .i_tdata(o_tdata_i1), 570 .i_tvalid(o_tvalid_i1 && ~supress_reads), 571 .i_tready(o_tready_i1), 572 // 573 .o_tdata(o_tdata_i2), 574 .o_tvalid(o_tvalid_i2), 575 .o_tready(o_tready_i2) 576 ); 577 578 // Pipeline flop before tlast extraction logic 579 axi_fifo_flop2 #(.WIDTH(DWIDTH)) output_pipe_i2 580 ( 581 .clk(dram_clk), 582 .reset(dram_reset), 583 .clear(clear), 584 // 585 .i_tdata(o_tdata_i2), 586 .i_tvalid(o_tvalid_i2), 587 .i_tready(o_tready_i2), 588 // 589 .o_tdata(o_tdata_i3), 590 .o_tvalid(o_tvalid_i3), 591 .o_tready(o_tready_i3) 592 ); 593 594 axi_extract_tlast #(.WIDTH(DWIDTH), .VALIDATE_CHECKSUM(0)) axi_extract_tlast_i ( 595 .clk(dram_clk), 596 .reset(dram_reset), 597 .clear(clear), 598 // 599 .i_tdata(o_tdata_i3), 600 .i_tvalid(o_tvalid_i3), 601 .i_tready(o_tready_i3), 602 // 603 .o_tdata(o_tdata_i4), 604 .o_tlast(o_tlast_i4), 605 .o_tvalid(o_tvalid_i4), 606 .o_tready(o_tready_i4), 607 // 608 .checksum_error() 609 ); 610 611 // Pipeline flop after tlast extraction logic 612 axi_fifo_flop2 #(.WIDTH(DWIDTH+1)) output_pipe_i3 613 ( 614 .clk(dram_clk), 615 .reset(dram_reset), 616 .clear(clear), 617 // 618 .i_tdata({o_tlast_i4,o_tdata_i4}), 619 .i_tvalid(o_tvalid_i4), 620 .i_tready(o_tready_i4), 621 // 622 .o_tdata({o_tlast_i5,o_tdata_i5}), 623 .o_tvalid(o_tvalid_i5), 624 .o_tready(o_tready_i5) 625 ); 626 627 wire write_out, read_out, empty_out, full_out; 628 assign o_tready_i5 = ~full_out; 629 assign write_out = o_tvalid_i5 & o_tready_i5; 630 assign o_tvalid_fifo = ~empty_out; 631 assign read_out = o_tvalid_fifo & o_tready_fifo; 632 wire [6:0] discard_i1; 633 634 fifo_short_2clk fifo_short_2clk_i1 ( 635 .rst(dram_reset), 636 .wr_clk(dram_clk), 637 .din({7'h0,o_tlast_i5,o_tdata_i5}), // input [71 : 0] din 638 .wr_en(write_out), // input wr_en 639 .full(full_out), // output full 640 .wr_data_count(), // output [9 : 0] wr_data_count 641 642 .rd_clk(bus_clk), // input rd_clk 643 .dout({discard_i1,o_tlast_fifo,o_tdata_fifo}), // output [71 : 0] dout 644 .rd_en(read_out), // input rd_en 645 .empty(empty_out), // output empty 646 .rd_data_count() // output [9 : 0] rd_data_count 647 ); 648 649 // 650 // Simple input timeout counter for now. 651 // Timeout count only increments when there is some data waiting to be written. 652 // 653 always @(posedge dram_clk) 654 if (dram_reset | clear) begin 655 input_timeout_count <= 9'd0; 656 input_timeout_triggered <= 1'b0; 657 end else if (input_timeout_reset) begin 658 input_timeout_count <= 9'd0; 659 input_timeout_triggered <= 1'b0; 660 end else if (input_timeout_count == set_timeout[8:0]) begin 661 input_timeout_triggered <= 1'b1; 662 end else if (input_state == INPUT_IDLE) begin 663 input_timeout_count <= input_timeout_count + ((occupied_input != 16'd0) ? 9'd1 : 9'd0); 664 end 665 666 // 667 // Wait for 16 entries in input FIFO to trigger DRAM write burst. 668 // Timeout can also trigger burst so fragments of data are not left to rot in the input FIFO. 669 // Also if enough data is present in the input FIFO to complete a burst upto the edge 670 // of a 4KByte page then immediately start the burst. 671 // 672 always @(posedge dram_clk) 673 if (dram_reset | clear) begin 674 input_state <= INPUT_IDLE; 675 write_addr <= set_fifo_base_addr & set_fifo_addr_mask; 676 input_timeout_reset <= 1'b0; 677 write_ctrl_valid <= 1'b0; 678 write_count <= 8'd0; 679 write_count_plus_one <= 9'd1; 680 update_write <= 1'b0; 681 end else 682 case (input_state) 683 // 684 // INPUT_IDLE. 685 // To start an input transfer to DRAM need: 686 // 1) Space in the DRAM FIFO 687 // and either 688 // 2) 256 entrys in the input FIFO 689 // or 690 // 3) Timeout waiting for more data. 691 // 692 INPUT_IDLE: begin 693 write_ctrl_valid <= 1'b0; 694 update_write <= 1'b0; 695 if (space[AWIDTH-3:8] != 'd0) begin // (space > 255): Space in the DRAM FIFO 696 if (occupied_input[15:8] != 'd0) begin // (occupied_input > 255): 256 or more entries in input FIFO 697 input_state <= INPUT1; 698 input_timeout_reset <= 1'b1; 699 // Calculate number of entries remaining until next 4KB page boundry is crossed minus 1. 700 // Note, units of calculation are 64bit wide words. Address is always 64bit alligned. 701 input_page_boundry <= {write_addr[AWIDTH-1:12],9'h1ff} - write_addr[AWIDTH-1:3]; 702 end else if (input_timeout_triggered) begin // input FIFO timeout waiting for new data. 703 input_state <= INPUT2; 704 input_timeout_reset <= 1'b1; 705 // Calculate number of entries remaining until next 4KB page boundry is crossed minus 1. 706 // Note, units of calculation are 64bit wide words. Address is always 64bit alligned. 707 input_page_boundry <= {write_addr[AWIDTH-1:12],9'h1ff} - write_addr[AWIDTH-1:3]; 708 end else begin 709 input_timeout_reset <= 1'b0; 710 input_state <= INPUT_IDLE; 711 end 712 end else begin 713 input_timeout_reset <= 1'b0; 714 input_state <= INPUT_IDLE; 715 end 716 end 717 // 718 // INPUT1. 719 // Caused by input FIFO reaching 256 entries. 720 // Request write burst of lesser of: 721 // 1) Entrys until page boundry crossed 722 // 2) 256. 723 // 724 INPUT1: begin 725 // Replicated write logic to break a read timing critical path for write_count 726 write_count <= (input_page_boundry[11:8] == 4'd0) ? input_page_boundry[7:0] : 8'd255; 727 write_count_plus_one <= (input_page_boundry[11:8] == 4'd0) ? ({1'b0,input_page_boundry[7:0]} + 9'd1) : 9'd256; 728 write_ctrl_valid <= 1'b1; 729 if (write_ctrl_ready) 730 input_state <= INPUT4; // Pre-emptive ACK 731 else 732 input_state <= INPUT3; // Wait for ACK 733 end 734 // 735 // INPUT2. 736 // Caused by timeout of input FIFO. (occupied_input was implicitly less than 256 last cycle) 737 // Request write burst of lesser of: 738 // 1) Entries until page boundry crossed 739 // 2) Entries in input FIFO 740 // 741 INPUT2: begin 742 // Replicated write logic to break a read timing critical path for write_count 743 write_count <= (input_page_boundry < ({3'h0,occupied_input[8:0]} - 12'd1)) ? input_page_boundry[7:0] : (occupied_input[8:0] - 9'd1); 744 write_count_plus_one <= (input_page_boundry < ({3'h0,occupied_input[8:0]} - 12'd1)) ? ({1'b0,input_page_boundry[7:0]} + 9'd1) : occupied_input[8:0]; 745 write_ctrl_valid <= 1'b1; 746 if (write_ctrl_ready) 747 input_state <= INPUT4; // Pre-emptive ACK 748 else 749 input_state <= INPUT3; // Wait for ACK 750 end 751 // 752 // INPUT3. 753 // Wait in this state for AXI4_DMA engine to accept transaction. 754 // 755 INPUT3: begin 756 if (write_ctrl_ready) begin 757 write_ctrl_valid <= 1'b0; 758 input_state <= INPUT4; // ACK 759 end else begin 760 write_ctrl_valid <= 1'b1; 761 input_state <= INPUT3; // Wait for ACK 762 end 763 end 764 // 765 // INPUT4. 766 // Wait here until write_ctrl_ready_deasserts. 767 // This is important as the next time it asserts we know that a write response was receieved. 768 INPUT4: begin 769 write_ctrl_valid <= 1'b0; 770 if (!write_ctrl_ready) 771 input_state <= INPUT5; // Move on 772 else 773 input_state <= INPUT4; // Wait for deassert 774 end 775 // 776 // INPUT5. 777 // Transaction has been accepted by AXI4 DMA engine. Now we wait for the re-assertion 778 // of write_ctrl_ready which signals that the AXI4 DMA engine has receieved a response 779 // for the whole write transaction and we assume that this means it is commited to DRAM. 780 // We are now free to update write_addr pointer and go back to idle state. 781 // 782 INPUT5: begin 783 write_ctrl_valid <= 1'b0; 784 if (write_ctrl_ready) begin 785 write_addr <= ((write_addr + (write_count_plus_one << 3)) & set_fifo_addr_mask_bar) | (write_addr & set_fifo_addr_mask); 786 input_state <= INPUT6; 787 update_write <= 1'b1; 788 end else begin 789 input_state <= INPUT5; 790 end 791 end 792 // 793 // INPUT6: 794 // Need to let space update before looking if there's more to do. 795 // 796 INPUT6: begin 797 input_state <= INPUT_IDLE; 798 update_write <= 1'b0; 799 end 800 801 default: 802 input_state <= INPUT_IDLE; 803 endcase // case(input_state) 804 805 806 // 807 // Simple output timeout counter for now 808 // 809 always @(posedge dram_clk) 810 if (dram_reset | clear) begin 811 output_timeout_count <= 9'd0; 812 output_timeout_triggered <= 1'b0; 813 end else if (output_timeout_reset) begin 814 output_timeout_count <= 9'd0; 815 output_timeout_triggered <= 1'b0; 816 end else if (output_timeout_count == set_timeout[8:0]) begin 817 output_timeout_triggered <= 1'b1; 818 end else if (output_state == OUTPUT_IDLE) begin 819 output_timeout_count <= output_timeout_count + ((occupied != 'd0) ? 9'd1 : 9'd0); 820 end 821 822 823 // 824 // Wait for 64 entries in main FIFO to trigger DRAM read burst. 825 // Timeout can also trigger burst so fragments of data are not left to rot in the main FIFO. 826 // Also if enough data is present in the main FIFO to complete a burst upto the edge 827 // of a 4KByte page then immediately start the burst. 828 // 829 always @(posedge dram_clk) 830 if (dram_reset | clear) begin 831 output_state <= OUTPUT_IDLE; 832 read_addr <= set_fifo_base_addr & set_fifo_addr_mask; 833 output_timeout_reset <= 1'b0; 834 read_ctrl_valid <= 1'b0; 835 read_count <= 8'd0; 836 read_count_plus_one <= 9'd1; 837 update_read <= 1'b0; 838 end else 839 case (output_state) 840 // 841 // OUTPUT_IDLE. 842 // To start an output tranfer from DRAM 843 // 1) Space in the small output FIFO 844 // and either 845 // 2) 256 entrys in the DRAM FIFO 846 // or 847 // 3) Timeout waiting for more data. 848 // 849 OUTPUT_IDLE: begin 850 read_ctrl_valid <= 1'b0; 851 update_read <= 1'b0; 852 if (space_output[15:8] != 'd0) begin // (space_output > 255): Space in the output FIFO. 853 if (occupied[AWIDTH-3:8] != 'd0) begin // (occupied > 255): 64 or more entrys in main FIFO 854 output_state <= OUTPUT1; 855 output_timeout_reset <= 1'b1; 856 // Calculate number of entries remaining until next 4KB page boundry is crossed minus 1. 857 // Note, units of calculation are 64bit wide words. Address is always 64bit alligned. 858 output_page_boundry <= {read_addr[AWIDTH-1:12],9'h1ff} - read_addr[AWIDTH-1:3]; 859 end else if (output_timeout_triggered) begin // output FIFO timeout waiting for new data. 860 output_state <= OUTPUT2; 861 output_timeout_reset <= 1'b1; 862 // Calculate number of entries remaining until next 4KB page boundry is crossed minus 1. 863 // Note, units of calculation are 64bit wide words. Address is always 64bit alligned. 864 output_page_boundry <= {read_addr[AWIDTH-1:12],9'h1ff} - read_addr[AWIDTH-1:3]; 865 end else begin 866 output_timeout_reset <= 1'b0; 867 output_state <= OUTPUT_IDLE; 868 end 869 end else begin 870 output_timeout_reset <= 1'b0; 871 output_state <= OUTPUT_IDLE; 872 end 873 end // case: OUTPUT_IDLE 874 // 875 // OUTPUT1. 876 // Caused by main FIFO reaching 256 entries. 877 // Request read burst of lesser of lesser of: 878 // 1) Entrys until page boundry crossed 879 // 2) 256. 880 // 881 OUTPUT1: begin 882 // Replicated write logic to break a read timing critical path for read_count 883 read_count <= (output_page_boundry[11:8] == 4'd0) ? output_page_boundry[7:0] : 8'd255; 884 read_count_plus_one <= (output_page_boundry[11:8] == 4'd0) ? ({1'b0,output_page_boundry[7:0]} + 9'd1) : 9'd256; 885 read_ctrl_valid <= 1'b1; 886 if (read_ctrl_ready) 887 output_state <= OUTPUT4; // Pre-emptive ACK 888 else 889 output_state <= OUTPUT3; // Wait for ACK 890 end 891 // 892 // OUTPUT2. 893 // Caused by timeout of main FIFO 894 // Request read burst of lesser of: 895 // 1) Entries until page boundry crossed 896 // 2) Entries in main FIFO 897 // 898 OUTPUT2: begin 899 // Replicated write logic to break a read timing critical path for read_count 900 read_count <= (output_page_boundry < occupied_minus_one) ? output_page_boundry[7:0] : occupied_minus_one[7:0]; 901 read_count_plus_one <= (output_page_boundry < occupied_minus_one) ? ({1'b0,output_page_boundry[7:0]} + 9'd1) : {1'b0, occupied[7:0]}; 902 read_ctrl_valid <= 1'b1; 903 if (read_ctrl_ready) 904 output_state <= OUTPUT4; // Pre-emptive ACK 905 else 906 output_state <= OUTPUT3; // Wait for ACK 907 end 908 // 909 // OUTPUT3. 910 // Wait in this state for AXI4_DMA engine to accept transaction. 911 // 912 OUTPUT3: begin 913 if (read_ctrl_ready) begin 914 read_ctrl_valid <= 1'b0; 915 output_state <= OUTPUT4; // ACK 916 end else begin 917 read_ctrl_valid <= 1'b1; 918 output_state <= OUTPUT3; // Wait for ACK 919 end 920 end 921 // 922 // OUTPUT4. 923 // Wait here unitl read_ctrl_ready_deasserts. 924 // This is important as the next time it asserts we know that a read response was receieved. 925 OUTPUT4: begin 926 read_ctrl_valid <= 1'b0; 927 if (!read_ctrl_ready) 928 output_state <= OUTPUT5; // Move on 929 else 930 output_state <= OUTPUT4; // Wait for deassert 931 end 932 // 933 // OUTPUT5. 934 // Transaction has been accepted by AXI4 DMA engine. Now we wait for the re-assertion 935 // of read_ctrl_ready which signals that the AXI4 DMA engine has receieved a last signal and good response 936 // for the whole read transaction. 937 // We are now free to update read_addr pointer and go back to idle state. 938 // 939 OUTPUT5: begin 940 read_ctrl_valid <= 1'b0; 941 if (read_ctrl_ready) begin 942 read_addr <= ((read_addr + (read_count_plus_one << 3)) & set_fifo_addr_mask_bar) | (read_addr & set_fifo_addr_mask); 943 output_state <= OUTPUT6; 944 update_read <= 1'b1; 945 end else begin 946 output_state <= OUTPUT5; 947 end 948 end // case: OUTPUT5 949 // 950 // OUTPUT6. 951 // Need to get occupied value updated before checking if there's more to do. 952 // 953 OUTPUT6: begin 954 update_read <= 1'b0; 955 output_state <= OUTPUT_IDLE; 956 end 957 958 default: 959 output_state <= OUTPUT_IDLE; 960 endcase // case(output_state) 961 962 // 963 // Count number of used entries in main DRAM FIFO. 964 // Note that this is expressed in units of 64bit wide words. 965 // 966 always @(posedge dram_clk) 967 if (dram_reset | clear) begin 968 occupied <= 'd0; 969 occupied_minus_one <= {(AWIDTH-2){1'b1}}; 970 end else begin 971 occupied <= occupied + (update_write ? write_count_plus_one : 9'd0) - (update_read ? read_count_plus_one : 9'd0); 972 occupied_minus_one <= occupied_minus_one + (update_write ? write_count_plus_one : 9'd0) - (update_read ? read_count_plus_one : 9'd0); 973 end 974 975 always @(posedge dram_clk) 976 if (dram_reset | clear) 977 space <= set_fifo_addr_mask_bar[AWIDTH-1:3] & ~('d63); // Subtract 64 from space to make allowance for read/write reordering in DRAM controller 978 else 979 space <= space - (update_write ? write_count_plus_one : 9'd0) + (update_read ? read_count_plus_one : 9'd0); 980 981 // 982 // Instamce of axi_dma_master 983 // 984 axi_dma_master axi_dma_master_i 985 ( 986 .aclk(dram_clk), // input aclk 987 .areset(dram_reset | clear), // input aresetn 988 // Write control 989 .m_axi_awid(m_axi_awid), // input [0 : 0] m_axi_awid 990 .m_axi_awaddr(m_axi_awaddr), // input [31 : 0] m_axi_awaddr 991 .m_axi_awlen(m_axi_awlen), // input [7 : 0] m_axi_awlen 992 .m_axi_awsize(m_axi_awsize), // input [2 : 0] m_axi_awsize 993 .m_axi_awburst(m_axi_awburst), // input [1 : 0] m_axi_awburst 994 .m_axi_awvalid(m_axi_awvalid), // input m_axi_awvalid 995 .m_axi_awready(m_axi_awready), // output m_axi_awready 996 .m_axi_awlock(m_axi_awlock), 997 .m_axi_awcache(m_axi_awcache), 998 .m_axi_awprot(m_axi_awprot), 999 .m_axi_awqos(m_axi_awqos), 1000 .m_axi_awregion(m_axi_awregion), 1001 .m_axi_awuser(m_axi_awuser), 1002 // Write Data 1003 .m_axi_wdata(m_axi_wdata), // input [63 : 0] m_axi_wdata 1004 .m_axi_wstrb(m_axi_wstrb), // input [7 : 0] m_axi_wstrb 1005 .m_axi_wlast(m_axi_wlast), // input m_axi_wlast 1006 .m_axi_wvalid(m_axi_wvalid), // input m_axi_wvalid 1007 .m_axi_wready(m_axi_wready), // output m_axi_wready 1008 .m_axi_wuser(m_axi_wuser), 1009 // Write Response 1010 .m_axi_bid(m_axi_bid), // output [0 : 0] m_axi_bid 1011 .m_axi_bresp(m_axi_bresp), // output [1 : 0] m_axi_bresp 1012 .m_axi_bvalid(m_axi_bvalid), // output m_axi_bvalid 1013 .m_axi_bready(m_axi_bready), // input m_axi_bready 1014 .m_axi_buser(m_axi_buser), 1015 // Read Control 1016 .m_axi_arid(m_axi_arid), // input [0 : 0] m_axi_arid 1017 .m_axi_araddr(m_axi_araddr), // input [31 : 0] m_axi_araddr 1018 .m_axi_arlen(m_axi_arlen), // input [7 : 0] m_axi_arlen 1019 .m_axi_arsize(m_axi_arsize), // input [2 : 0] m_axi_arsize 1020 .m_axi_arburst(m_axi_arburst), // input [1 : 0] m_axi_arburst 1021 .m_axi_arvalid(m_axi_arvalid), // input m_axi_arvalid 1022 .m_axi_arready(m_axi_arready), // output m_axi_arready 1023 .m_axi_arlock(m_axi_arlock), 1024 .m_axi_arcache(m_axi_arcache), 1025 .m_axi_arprot(m_axi_arprot), 1026 .m_axi_arqos(m_axi_arqos), 1027 .m_axi_arregion(m_axi_arregion), 1028 .m_axi_aruser(m_axi_aruser), 1029 // Read Data 1030 .m_axi_rid(m_axi_rid), // output [0 : 0] m_axi_rid 1031 .m_axi_rdata(m_axi_rdata), // output [63 : 0] m_axi_rdata 1032 .m_axi_rresp(m_axi_rresp), // output [1 : 0] m_axi_rresp 1033 .m_axi_rlast(m_axi_rlast), // output m_axi_rlast 1034 .m_axi_rvalid(m_axi_rvalid), // output m_axi_rvalid 1035 .m_axi_rready(m_axi_rready), // input m_axi_rready 1036 .m_axi_ruser(m_axi_ruser), 1037 // 1038 // DMA interface for Write transaction 1039 // 1040 .write_addr({{(32-AWIDTH){1'b0}}, write_addr}), // Byte address for start of write transaction (should be 64bit alligned) 1041 .write_count(write_count), // Count of 64bit words to write. 1042 .write_ctrl_valid(write_ctrl_valid), 1043 .write_ctrl_ready(write_ctrl_ready), 1044 .write_data(i_tdata_input), 1045 .write_data_valid(i_tvalid_input), 1046 .write_data_ready(i_tready_input), 1047 // 1048 // DMA interface for Read 1049 // 1050 .read_addr({{(32-AWIDTH){1'b0}}, read_addr}), // Byte address for start of read transaction (should be 64bit alligned) 1051 .read_count(read_count), // Count of 64bit words to read. 1052 .read_ctrl_valid(read_ctrl_valid), 1053 .read_ctrl_ready(read_ctrl_ready), 1054 .read_data(o_tdata_output), 1055 .read_data_valid(o_tvalid_output), 1056 .read_data_ready(o_tready_output), 1057 // 1058 // Debug 1059 // 1060 .debug() 1061 ); 1062 1063 //ila_axi_dma_fifo inst_ila ( 1064 // .clk(ce_clk), // input wire clk 1065 // .probe0(rb_bist_status), // input wire [3:0] probe0 channel 0 1066 // .probe1(), // input wire [3:0] probe0 channel 0 1067 //); 1068 1069 1070 1071 1072 endmodule // axi_dma_fifo 1073 1074