1// 2// Copyright 2011 Ettus Research LLC 3// Copyright 2018-2019 Ettus Research, a National Instruments Brand 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7// The purpose of this module is to synchronize a reset from one clock domain 8// to another. The reset_in signal must be driven by a glitch-free source. 9// 10 11module reset_sync ( 12 // clock for the output reset 13 input clk, 14 // glitch-free input reset 15 input reset_in, 16 // output reset in the clk domain 17 output reg reset_out); 18 19 wire reset_c; 20 21 synchronizer #( 22 // The input reset is async to the output clk domain... so timing should not be 23 // analyzed here! 24 .FALSE_PATH_TO_IN(1), 25 // Assert reset_out by default. When clk starts toggling the downstream logic will 26 // be in reset for at least 10 clk cycles. This allows the clock to settle (if needed) 27 // and the reset to propagate fully to all logic. 28 .INITIAL_VAL(1), 29 .STAGES(10) 30 ) reset_double_sync ( 31 .clk(clk), .rst(1'b0), .in(reset_in), .out(reset_c) 32 ); 33 34 always @(posedge clk) 35 reset_out <= reset_c; 36 37endmodule // reset_sync 38