1// 2// Copyright 2013 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7 8 9`timescale 500ps/1ps 10 11module pcie_iop2_msg_arbiter_tb(); 12 reg clk = 0; 13 reg reset = 1; 14 15 always #10 clk = ~clk; 16 17 initial begin 18 #100 reset = 0; 19 #200000; 20 $finish; 21 end 22 23 function [63:0] iop2_msg_write; 24 input [19:0] address; 25 input [31:0] data; 26 input half_wd; 27 begin 28 // {rd_response, wr_request, rd_request, half_word, 8'h00, address, data}; 29 iop2_msg_write = {1'b0, 1'b1, 1'b0, half_wd, 8'h00, address, data}; 30 end 31 endfunction // iop2_msg_write 32 33 function [63:0] iop2_msg_read; 34 input [19:0] address; 35 input half_wd; 36 begin 37 // {rd_response, wr_request, rd_request, half_word, 8'h00, address, data}; 38 iop2_msg_read = {1'b0, 1'b0, 1'b1, half_wd, 8'h00, address, 32'h0}; 39 end 40 endfunction // iop2_msg_read 41 42 reg [63:0] msgi_tdata; 43 wire [63:0] msgo_tdata; 44 wire msgo_tvalid, msgi_tready; 45 reg msgo_tready, msgi_tvalid; 46 47 wire [63:0] basic_regi_tdata, zpu_regi_tdata; 48 wire basic_regi_tvalid, zpu_regi_tvalid; 49 reg basic_regi_tready, zpu_regi_tready; 50 reg [63:0] basic_rego_tdata, zpu_rego_tdata; 51 reg basic_rego_tvalid, zpu_rego_tvalid; 52 wire basic_rego_tready, zpu_rego_tready; 53 54 initial begin 55 //@TODO: Make this a self-checking TB 56 while (reset) @(posedge clk); 57 58 msgo_tready <= 1; 59 basic_regi_tready <= 1; 60 @(posedge clk); 61 62 63 msgi_tdata <= iop2_msg_write(20'h0, 32'hDEAD, 0); 64 msgi_tvalid <= 1; 65 while (~msgi_tready) @(posedge clk); 66 msgi_tvalid <= 0; 67 @(posedge clk); 68 69 70 msgi_tdata <= iop2_msg_read(20'h00000, 0); 71 msgi_tvalid <= 1; 72 while (~msgi_tready) @(posedge clk); 73 msgi_tvalid <= 0; 74 @(posedge clk); 75 76 zpu_rego_tdata <= {1, 31'h0, 32'h12345678}; 77 zpu_rego_tvalid <= 1; 78 while (~zpu_rego_tready) @(posedge clk); 79 zpu_rego_tvalid <= 0; 80 81 82 83 end // initial begin 84 85 pcie_iop2_msg_arbiter #( 86 .E0_ADDR(20'h00000), .E0_MASK(20'hFFF00), //0x00000 - 0x000FF: Basic PCIe registers 87 .E1_ADDR(20'h00100), .E1_MASK(20'hFFF00), //0x00100 - 0x001FF: PCIe router registers 88 .E2_ADDR(20'h00200), .E2_MASK(20'hFFE00), //0x00200 - 0x003FF: DMA stream registers 89 .E3_ADDR(20'h40000), .E3_MASK(20'hC0000) //0x40000 - 0x7FFFF: Client address space 90 ) iop2_msg_arbiter ( 91 .clk(clk), .reset(reset), 92 //Master 93 .regi_tdata(msgi_tdata), .regi_tvalid(msgi_tvalid), .regi_tready(msgi_tready), 94 .rego_tdata(msgo_tdata), .rego_tvalid(msgo_tvalid), .rego_tready(msgo_tready), 95 //Endpoint 0 96 .e0_regi_tdata(basic_regi_tdata), .e0_regi_tvalid(basic_regi_tvalid), .e0_regi_tready(basic_regi_tready), 97 .e0_rego_tdata(basic_rego_tdata), .e0_rego_tvalid(basic_rego_tvalid), .e0_rego_tready(basic_rego_tready), 98 //Endpoint 1 99 .e1_regi_tdata(), .e1_regi_tvalid(), .e1_regi_tready(1'b1), 100 .e1_rego_tdata(64'h0), .e1_rego_tvalid(1'b0), .e1_rego_tready(), 101 //Endpoint 2 102 .e2_regi_tdata(), .e2_regi_tvalid(), .e2_regi_tready(1'b1), 103 .e2_rego_tdata(64'h0), .e2_rego_tvalid(1'b0), .e2_rego_tready(), 104 //Endpoint 3 105 .e3_regi_tdata(zpu_regi_tdata), .e3_regi_tvalid(zpu_regi_tvalid), .e3_regi_tready(zpu_regi_tready), 106 .e3_rego_tdata(zpu_rego_tdata), .e3_rego_tvalid(zpu_rego_tvalid), .e3_rego_tready(zpu_rego_tready) 107 ); 108 109 110endmodule 111