1// 2// Copyright 2011 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7 8 9 10 11module simple_gemac_tb; 12`include "eth_tasks.v" 13 14 reg clk = 0; 15 reg reset = 1; 16 17 initial #1000 reset = 0; 18 always #50 clk = ~clk; 19 20 wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; 21 wire [7:0] GMII_RXD, GMII_TXD; 22 23 wire rx_valid, rx_error, rx_ack; 24 wire tx_ack, tx_valid, tx_error; 25 26 wire [7:0] rx_data, tx_data; 27 28 reg [15:0] pause_time; 29 reg pause_req = 0; 30 31 wire GMII_RX_CLK = GMII_GTX_CLK; 32 33 reg [7:0] FORCE_DAT_ERR = 0; 34 reg FORCE_ERR = 0; 35 36 // Loopback 37 assign GMII_RX_DV = GMII_TX_EN; 38 assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; 39 assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; 40 41 wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6; 42 wire [47:0] mcast_addr = 0; 43 wire pass_ucast =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0; 44 45 simple_gemac simple_gemac 46 (.clk125(clk), .reset(reset), 47 .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), 48 .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), 49 .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), 50 .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), 51 .pause_req(pause_req), .pause_time(pause_time), .pause_en(1), 52 .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), 53 .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 54 .pass_pause(pass_pause), .pass_all(pass_all), 55 .rx_clk(rx_clk), .rx_data(rx_data), 56 .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), 57 .tx_clk(tx_clk), .tx_data(tx_data), 58 .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack) 59 ); 60 61 wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; 62 wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2; 63 reg rx_ll_dst_rdy2 = 1; 64 wire [7:0] rx_ll_data, rx_ll_data2; 65 wire rx_ll_error, rx_ll_error2; 66 67 rxmac_to_ll8 rx_adapt 68 (.clk(clk), .reset(reset), .clear(0), 69 .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), 70 .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), 71 .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); 72 73 ll8_shortfifo rx_sfifo 74 (.clk(clk), .reset(reset), .clear(0), 75 .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), 76 .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), 77 .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), 78 .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); 79 80 wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; 81 reg tx_ll_sof2=0, tx_ll_eof2=0; 82 reg tx_ll_src_rdy2 = 0; 83 wire tx_ll_dst_rdy2; 84 wire [7:0] tx_ll_data; 85 reg [7:0] tx_ll_data2 = 0; 86 wire tx_ll_error; 87 wire tx_ll_error2 = 0; 88 89 ll8_shortfifo tx_sfifo 90 (.clk(clk), .reset(reset), .clear(clear), 91 .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), 92 .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), 93 .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), 94 .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); 95 96 ll8_to_txmac ll8_to_txmac 97 (.clk(clk), .reset(reset), .clear(clear), 98 .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), 99 .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), 100 .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); 101 102 initial $dumpfile("simple_gemac_tb.vcd"); 103 initial $dumpvars(0,simple_gemac_tb); 104 105 integer i; 106 reg [7:0] pkt_rom[0:65535]; 107 reg [1023:0] ROMFile; 108 109 initial 110 for (i=0;i<65536;i=i+1) 111 pkt_rom[i] <= 8'h0; 112 113 initial 114 begin 115 @(negedge reset); 116 repeat (10) 117 @(posedge clk); 118 SendFlowCtrl(16'h0007); // Send flow control 119 @(posedge clk); 120 #30000; 121 @(posedge clk); 122 SendFlowCtrl(16'h0009); // Increas flow control before it expires 123 #10000; 124 @(posedge clk); 125 SendFlowCtrl(16'h0000); // Cancel flow control before it expires 126 @(posedge clk); 127 128 SendPacket_to_ll8(8'hAA,10); // This packet gets dropped by the filters 129 repeat (10) 130 @(posedge clk); 131 132 SendPacketFromFile_ll8(60,0,0); // The rest are valid packets 133 repeat (10) 134 @(posedge clk); 135 136 SendPacketFromFile_ll8(61,0,0); 137 repeat (10) 138 @(posedge clk); 139 SendPacketFromFile_ll8(62,0,0); 140 repeat (10) 141 @(posedge clk); 142 SendPacketFromFile_ll8(63,0,0); 143 repeat (1) 144 @(posedge clk); 145 SendPacketFromFile_ll8(64,0,0); 146 repeat (10) 147 @(posedge clk); 148 SendPacketFromFile_ll8(59,0,0); 149 repeat (1) 150 @(posedge clk); 151 SendPacketFromFile_ll8(58,0,0); 152 repeat (1) 153 @(posedge clk); 154 SendPacketFromFile_ll8(100,0,0); 155 repeat (1) 156 @(posedge clk); 157 SendPacketFromFile_ll8(200,150,30); // waiting 14 empties the fifo, 15 underruns 158 repeat (1) 159 @(posedge clk); 160 SendPacketFromFile_ll8(100,0,30); 161 #10000 $finish; 162 end 163 164 // Force a CRC error 165 initial 166 begin 167 #90000; 168 @(posedge clk); 169 FORCE_DAT_ERR <= 8'h10; 170 @(posedge clk); 171 FORCE_DAT_ERR <= 8'h00; 172 end 173 174 // Force an RX_ER error (i.e. link loss) 175 initial 176 begin 177 #116000; 178 @(posedge clk); 179 FORCE_ERR <= 1; 180 @(posedge clk); 181 FORCE_ERR <= 0; 182 end 183 184 // Cause receive fifo to fill, causing an RX overrun 185 initial 186 begin 187 #126000; 188 @(posedge clk); 189 rx_ll_dst_rdy2 <= 0; 190 repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows 191 @(posedge clk); 192 rx_ll_dst_rdy2 <= 1; 193 end 194 195 // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun 196 // Still need to test: CRC errors on Pause Frames 197 198 always @(posedge clk) 199 if(rx_ll_src_rdy2 & rx_ll_dst_rdy2) 200 begin 201 if(rx_ll_sof2 & ~rx_ll_eof2) 202 $display("RX-PKT-START %d",$time); 203 $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2); 204 if(rx_ll_eof2 & ~rx_ll_sof2) 205 $display("RX-PKT-END %d",$time); 206 end 207 208endmodule // simple_gemac_tb 209