1/////////////////////////////////////////////////////////////////////////////// 2// Copyright (c) 2013 Xilinx, Inc. 3// All Rights Reserved 4/////////////////////////////////////////////////////////////////////////////// 5// ____ ____ 6// / /\/ / 7// /___/ \ / Vendor : Xilinx 8// \ \ \/ Version : 14.4 9// \ \ Application: Xilinx CORE Generator 10// / / Filename : chipscope_ila_128.v 11// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013 12// \ \ / \ 13// \___\/\___\ 14// 15// Design Name: Verilog Synthesis Wrapper 16/////////////////////////////////////////////////////////////////////////////// 17// This wrapper is used to integrate with Project Navigator and PlanAhead 18 19`timescale 1ns/1ps 20 21module chipscope_ila_128( 22 CONTROL, 23 CLK, 24 TRIG0) /* synthesis syn_black_box syn_noprune=1 */; 25 26 27inout [35 : 0] CONTROL; 28input CLK; 29input [127 : 0] TRIG0; 30 31endmodule 32